[Cryptech Tech] Alpha layout done (not a joke)

[Pavel Shatov]

On 02.04.2016 9:43, Jacob wrote:
>
> Additional comments:
>

Jacob, thank you very much for your comments and for fiducial patterns!

> 0. I am not looking at the layout with Altium but with another program,
> so I may be mistaken here, but it appears that the Gerber files for the
> Power_Plane were generated without the actual plane data for the
> islands(I assume those are positive planes) - just with the contour
> lines of the plane region. See for example missing FPGA 1.0V plane data
> on inner layer #4 in the Gerber file set.

As far as I remember, power and ground layers were generated with 
negative plane option turned on. I think we will re-generate everything 
using positive planes for consistency.

> 1. Under the analog noise circuitry you do keep out the GND on inner
> layer #1 (a good thing), but no keep-out there for GND on inner layer #6
> nor for the power planes.

Ok, will fix.

> 2. I guess that supposedly there are 4 mechanical mounting holes at the
> 4 corners of the board. However, only the bottom two are proper holes.
> The top 2 are not.

Well, that's how Intel's 3D model got imported into Altium. The two top 
holes are actually not round, but oval and they are part of board 
outline. The bottom two holes are just regular unplated drills. Do you 
suggest removing the two top holes from board outline and moving them to 
a new unplated milling contour?

> 3. Most of the large vias that come out of the decoupling capacitors are
> too close to comfort to the capacitor pads. In many cases the clearance
> between the soldermask of the decap pad and the via hole is 4 mil
> (0.1mm) - a border line case that with the slightest manufacturing
> deviation will render the gap w/o solder mask (not a good thing).

Jacob, I'm sorry, could you please explain this a a bit? Large vias (I'm 
assume you're talking about 0.5/1.0mm hole/pad ones) will be filled 
according to IPC 4761 Type VII ("via-in-pad").

> 4. Via on U8's pad should be moved away. See attached pic.

Ok, will fix.

>
> 5. I suggest to fill in with GND/PWR planes the large empty areas in
> inner layers - good for electrical performance and for etching
> uniformity in the mfg. process.

Yes, I hear it makes the board more resistant to delamination, will fix.

> 6. A nit: The FPGA JTAG table nomenclature is rotated 180 deg from other
> text on board.

Hm, why not fix what takes 5 seconds to fix? :)


-- 
With best regards,
Pavel Shatov