[Cryptech Tech] [Cryptech-Commits] [core/platform/novena] 21/21: Sick hacks to compensate for sparse MUX within TRNG core.

[Bernd Paysan]

Am 30. September 2015 01:54:03 GMT+08:00, schrieb Randy Bush <randy at psg.com>:
>> 1) Just leave everything as it is right now with mixed resets.
>> 
>> 2) We start a voting process and decide, what kind of reset we will
>be 
>> using from now on. Everyone will then modify his cores accordingly.
>> 
>> 3) Someone will take responsibility and decide for the whole team,
>what 
>> kind of reset is the right one for us. Again everyone will then
>modify 
>> his cores accordingly.
>
>you, rob, and joachim please crawl in a corner, discuss, and declare
>result.
>
>randy
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I don't know where this religious part about resets originates from; in reality, your average ASIC and FPGA flip-flop has an async active low input for reset. Using that means least amount of resources and confusion. It's just like the egg thing mentioned in Gulliver's travels: the bubble normally is on the big end, and therefore opening it there is easier. Religious wars started, nonetheless. 

Of course, you must not activate the clock before reset goes away (easy). But for sync reset, it's just the other way round: you must make sure there is an active clock before reset goes away, which is about the same effort. For I/Os with a defined value at startup, async is the only possible choice. And active low, because 0V is the only reliably available voltage at startup (not applicable for FPGAs).

The reset is only for startup, never for active circuit logic (unless you really  know what you are doing ;-), therefore, every later transition must be synchronous.
-- 
Bernd Paysan
"If you want it done right, you have to do it yourself"
net2o ID: kQusJzA;7*?t=uy at X}1GWr!+0qqp_Cn176t4(dQ*
http://bernd-paysan.de/
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