[Cryptech Tech] [Cryptech-Commits] [core/platform/novena] 21/21: Sick hacks to compensate for sparse MUX within TRNG core.

[Joachim Strömbergson]

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Aloha!

Rob Austein wrote:
> So, to date, the control register has acted as a command port to
> which we send a control opcode, with a slightly weird encoding of
> that opcode such that it can be parsed as bit flags if one prefers
> that.

Any suggestion on less weird encoding?


> Is there some condition you envision under which the FPGA would
> light the access violation error status bit but then go and do
> whatever it was the software had requested anyway?  My assumption had
> been that lighting that error bit meant that the operation had
> failed, so we're going to have to start over, which is going to
> involve setting the control word to some new value anyway.

The error we are talking about is an api access error. Reading from an
undefined API address for instance would imho not imply that the current
operation in the core has failed. In that case the only side effect
would be that the error bit has been set.


>> Just to clear confusion:
>> 
>> (1) Some access violation happens -> error bit in STATUS reg is
>> set.
>> 
>> (2) SW writes a <0/1> to error bit in CONTROL reg to clear bit in
>> STATUS reg.
>> 
>> (3) Error bit is cleared in the next cycle.
> 
> And core is now waiting for me to start a new operation, right?

Not necessarily no.

> Don't particularly care what opcode (or bit, if you prefer to think
> of it that way) we use so long as it's consistent.

See other mail re bits in the status register.

- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
========================================================================
 Joachim Strömbergson          Secworks AB          joachim at secworks.se
========================================================================
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