[Cryptech Tech] [Cryptech-Commits] [core/platform/novena] 21/21: Sick hacks to compensate for sparse MUX within TRNG core.

[Joachim Strömbergson]

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Aloha!

Pavel Shatov wrote:
> Reset is not strictly required for startup in an FPGA, since you can 
> write something like reg x = 1'b0 or reg y = 1'b1. Some people still 
> prefer to assign default values to registers using reset, but again 
> there's no point in doing it asynchronously.

Not having to defined reset values (esp zero) is due to the registers
being cleared as part of the config. But for ASIC design and for a lot
of tools (linters, simualtors), not having a defined value when reset is
released is bad practice in general and is often flagged.

Since we are stating that our code is not specifically limited for
FPGAs, we should IMHO have reset clauses of registers.

- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
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 Joachim Strömbergson          Secworks AB          joachim at secworks.se
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