[Cryptech Tech] [Cryptech-Commits] [core/platform/novena] 21/21: Sick hacks to compensate for sparse MUX within TRNG core.

[Rob Austein]

While we're talking about redoing the TRNG core's address map anyway:
perhaps we could also whack the ADDR and STATUS offsets to match what
every other core uses?  For every other core, CTRL is 0x08 and status
is 0x09, but for the RNG cores, CTRL is 0x10 and STATUS is 0x11.

If we could manage consistency on this sort of thing, it would allow
us to stop passing within-core address offsets to the low-level API
calls that play with the control and status bits.

That is, with this change, the new low-level API could be just:

  hal_io_wait_valid(const hal_core_t *);

whereas, with the current inconsistency, it has to be:

  hal_io_wait_valid(const hal_core_t *, const hal_addr_t);

to handle different cores keeping the same bits in different places.