[Cryptech Tech] [Cryptech-Commits] [core/platform/novena] 21/21: Sick hacks to compensate for sparse MUX within TRNG core.

[Basil Dolmatov]

Agree with Rob

Отправлено с iPhone

> 30 сент. 2015 г., в 16:14, Rob Austein <sra at hactrn.net> написал(а):
> 
> Assuming I understood you correctly, there would appear to be three
> basic options here:
> 
> 1) Error wires that trigger some kind of hardware condition
>   (interrupt?) in the main CPU;
> 
> 2) Error status bits which the main CPU has to poll; or
> 
> 3) No error signal.
> 
> Interrupt handlers are tricky; in practice, the safest thing to do in
> an interrupt handler is usually just to set a status bit.  There are
> situations where a hardware interrupt is the right answer, but just
> signalling a condition to software that has to poll for other
> conditions anyway is probably not one of them.
> 
> So my preference, if we're trying to signal errors from FPGA to CPU,
> would be option (2).  We already have a status word with READY and
> VALID bits as part of the standard core API, I'd just add an ERROR bit
> to that word (or bits, if we want to have actual codes instead of just
> a single flag).  Software would have to poll for this, but we have to
> poll for status after most operations anyway, so this isn't a change.
> 
> Have I missed anything here?
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