[Cryptech Tech] sha3 core code problems

Bernd Paysan bernd at net2o.de
Wed Mar 11 14:11:29 UTC 2015


Am Mittwoch, 11. März 2015, 13:47:52 schrieb Joachim Strömbergson:
> Aloha!
> 
> Bernd:
> I've tried to build a version of the Novena FPGA with the new sha3 core.
> Unfortunately, ISE don't support the parameterization used in the code.
> ISE stops with:
> 
> Parsing module <sha3>.
> ERROR:HDLCompiler:939 -
> "\\psf\home\Sandbox\external\cryptech\core\sha3\src\rtl\sha3.v" Line 49:
> Single value range is not allowed in this mode of verilog

You then have to undo the parametrization, i.e. replase "bus" with whatever 
bus width you actually want - e.g. 2 for 32 bits.

> Quartus can parse the code with a lot of warnings. But when trying to
> build the core for Cyclone IV GX, the build never completes.
> 
> Warning (10230): Verilog HDL assignment warning at sha3.v(58): truncated
> value with size 64 to match size of target (32)
> 
> Warning (10230): Verilog HDL assignment warning at sha3.v(97): truncated
> value with size 128 to match size of target (64)
> 
> Warning (10230): Verilog HDL assignment warning at sha3.v(105):
> truncated value with size 120 to match size of target (32)
> 
> Warning (10230): Verilog HDL assignment warning at sha3.v(106):
> truncated value with size 192 to match size of target (128)
> 
> Warning (10230): Verilog HDL assignment warning at sha3.v(118):
> truncated value with size 1536 to match size of target (64)

That's strange.  What version of Quartus is that?  I use 13.0sp1, because 13.x 
is the last one to support the Cyclone II of my DE1 board.  All these 
truncation values can be ignored.  Unfortunately, they forgot to add an easy 
way to truncate stuff in Verilog, see here for ugly solutions:

http://electronics.stackexchange.com/questions/67281/how-to-truncate-an-expression-bit-width-in-verilog

The "obvious" one (just adding [upper:lower] to an expression) unfortunately 
isn't possible.  Neither are variables in a bit range select.  The arbitrary 
and unjustified limitations of Verilog do hurt on that kind of code.

-- 
Bernd Paysan
"If you want it done right, you have to do it yourself"
http://bernd-paysan.de/
net2o ID: kQusJzA;7*?t=uy at X}1GWr!+0qqp_Cn176t4(dQ*



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