[Cryptech Tech] sha3 core code problems

[Joachim Strömbergson]

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Aloha!

Bernd:
I've tried to build a version of the Novena FPGA with the new sha3 core.
Unfortunately, ISE don't support the parameterization used in the code.
ISE stops with:

Parsing module <sha3>.
ERROR:HDLCompiler:939 -
"\\psf\home\Sandbox\external\cryptech\core\sha3\src\rtl\sha3.v" Line 49:
Single value range is not allowed in this mode of verilog

ERROR:HDLCompiler:598 -
"\\psf\home\Sandbox\external\cryptech\core\sha3\src\rtl\sha3.v" Line 43:
Module <sha3> ignored due to previous errors.
Verilog file
\\psf\home\Sandbox\external\cryptech\core\sha3\src\rtl\sha3.v ignored
due to errors


The linter in Verilator does not like the code either:

%Warning-WIDTH: sha3.v:57: Operator ASSIGN expects 32 bits on the Assign
RHS, but Assign RHS's ARRAYSEL generates 64 bits.

%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around
source to disable this message.

%Warning-WIDTH: sha3.v:58: Operator ASSIGN expects 32 bits on the Assign
RHS, but Assign RHS's SHIFTR generates 64 bits.

%Warning-WIDTH: sha3.v:59: Operator ASSIGN expects 32 bits on the Assign
RHS, but Assign RHS's SHIFTR generates 64 bits.

%Warning-WIDTH: sha3.v:60: Operator ASSIGN expects 32 bits on the Assign
RHS, but Assign RHS's SHIFTR generates 64 bits.

%Warning-WIDTH: sha3.v:97: Operator XOR expects 128 bits on the LHS, but
LHS's ARRAYSEL generates 64 bits.

%Warning-WIDTH: sha3.v:97: Operator AND expects 128 bits on the RHS, but
RHS's CONST '64'hffffffffffffffff' generates 64 bits.

%Warning-WIDTH: sha3.v:97: Operator ASSIGN expects 64 bits on the Assign
RHS, but Assign RHS's XOR generates 128 bits.

%Warning-WIDTH: sha3.v:105: Operator AND expects 120 bits on the RHS,
but RHS's CONST '5'h1f' generates 5 bits.

%Warning-WIDTH: sha3.v:105: Operator ASSIGN expects 32 bits on the
Assign RHS, but Assign RHS's AND generates 120 bits.

%Warning-WIDTH: sha3.v:106: Operator AND expects 144 bits on the RHS,
but RHS's CONST '6'h3f' generates 6 bits.

%Error: sha3.v:106: Unsupported: Shifting of by over 32-bit number isn't
supported. (This isn't a shift of 32 bits, but a shift of 2^32, or 4
billion!)

%Warning-WIDTH: sha3.v:106: Operator AND expects 128 bits on the RHS,
but RHS's CONST '64'hffffffffffffffff' generates 64 bits.

%Warning-WIDTH: sha3.v:106: Operator ASSIGN expects 128 bits on the
Assign RHS, but Assign RHS's REPLICATE generates 192 bits.

%Warning-WIDTH: sha3.v:118: Operator SUB expects 32 or 7 bits on the
RHS, but RHS's VARREF 'round' generates 5 bits.

%Warning-WIDTH: sha3.v:118: Operator XOR expects 1536 bits on the LHS,
but LHS's ARRAYSEL generates 64 bits.

%Warning-WIDTH: sha3.v:118: Operator AND expects 1536 bits on the RHS,
but RHS's CONST '64'hffffffffffffffff' generates 64 bits.

%Warning-WIDTH: sha3.v:118: Operator ASSIGN expects 64 bits on the
Assign RHS, but Assign RHS's XOR generates 1536 bits.

%Warning-WIDTH: sha3.v:142: Operator ASSIGNDLY expects 64 bits on the
Assign RHS, but Assign RHS's VARREF 'dinxor' generates 32 bits.

%Warning-WIDTH: sha3.v:148: Operator ASSIGNDLY expects 16 bits on the
Assign RHS, but Assign RHS's VARREF 'dinxor' generates 32 bits.

%Warning-WIDTH: sha3.v:149: Operator ASSIGNDLY expects 16 bits on the
Assign RHS, but Assign RHS's VARREF 'dinxor' generates 32 bits.

%Warning-WIDTH: sha3.v:150: Operator ASSIGNDLY expects 16 bits on the
Assign RHS, but Assign RHS's VARREF 'dinxor' generates 32 bits.

%Warning-WIDTH: sha3.v:151: Operator ASSIGNDLY expects 16 bits on the
Assign RHS, but Assign RHS's VARREF 'dinxor' generates 32 bits.
%Error: Exiting due to 1 error(s), 21 warning(s)


Quartus can parse the code with a lot of warnings. But when trying to
build the core for Cyclone IV GX, the build never completes.

Warning (10230): Verilog HDL assignment warning at sha3.v(58): truncated
value with size 64 to match size of target (32)

Warning (10230): Verilog HDL assignment warning at sha3.v(97): truncated
value with size 128 to match size of target (64)

Warning (10230): Verilog HDL assignment warning at sha3.v(105):
truncated value with size 120 to match size of target (32)

Warning (10230): Verilog HDL assignment warning at sha3.v(106):
truncated value with size 192 to match size of target (128)

Warning (10230): Verilog HDL assignment warning at sha3.v(118):
truncated value with size 1536 to match size of target (64)

- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
========================================================================
 Joachim Strömbergson          Secworks AB          joachim at secworks.se
========================================================================
-----BEGIN PGP SIGNATURE-----
Version: GnuPG/MacGPG2 v2
Comment: GPGTools - http://gpgtools.org
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/

iQIcBAEBCAAGBQJVADl4AAoJEF3cfFQkIuyN0CMQAIdz+N8M8jRzfyk85SJhfWbM
P8cggJuwQ6zob/F3446hsU2O6kaMxO699KWbAk0Uc0W65zRrImfzqUrhQVg08qwU
6gHRPIoY+fhFyRdet1qgZV13GGb0nw1KhkVswcZfKDdJigGCt3u6yLWXhstUYJ96
zOv1ItDpDWO2yE926exEHm6FMVeIB8hht1AyjPb0eA0w1E1UQvqzMHBLuK62iEtR
ZOuHHFVJt38BNISGG7meaaptRUfeMjkuVo6Y57ohc5JX3CyGQ3ltkzdMkKPAudgp
AygFuYKPaANskrE9J6Vuk9cmfhHDhFe8vpFySsxrs3ENNEizkJelN35GEDQ/652H
cZxJnNu3n75jhdyZMLIyBVFUDSw8+MkC1NEQzOCooFe93Sj1du4qZzdUxHC+UQTn
hdWle9hFHRIm3M+wCnr/kRwjjrRYJ/I3QIpwFwwx76m/obQCHo46SaS+9hEAZR9p
oWYR3z9+vB2K4bGAUvEVEfSHZ33bVidlXLMieBiuQUvTv1VRRpedWA3le0pmiPs7
VLg5oEGNSf6rkkio17OIWgmTK4cjLgkzr65fvTotRMwneXg5m1EPonIS42g/QGWT
T4lgbunYDSihecAY4xI/+vKTcCM92I7qOgIHZGD0Eu9NyEhoBYRsX7g32/N1KVtu
7ZAW5crVTpI6YrPG1P0/
=GQov
-----END PGP SIGNATURE-----