[Cryptech Tech] Novena dev-bridge board status

[Fredrik Thulin]

On Wednesday, June 24, 2015 12:17:06 AM Павел Шатов wrote:
...
> Fredrik, I've taken a look too. My thoughts are below.
> 
> 1. It is usually recommended to completely fill internal power/ground
> layers with polygons. It improves manufacturability of the board,
> because it will have constant thickness and will be less susceptible to
> delamination. I suggest filling empty space in the upper-left corner of
> internal power layer with small ground polygon (01.png)

Ok. Fascinating how a couple of mils here and there in a CAD program can have 
such real world implications.

> 2. I don't understand R9. RC filters must not be used to filter power
> rails, because you are effectively inserting a resistor in series with
> load, which causes voltage drop. Power rails must be filtered with LC
> filters. Instead of R9 an inductor can be used, or a ferrite bead maybe.

You know what - I was thinking the exact same thing yesterday about ferrite or 
inductor. I remember experimenting and simulating some to try and get rid of 
spikes I could see in the 5V rail from the Novena, but I need to re-visit this 
more thoroughly.

R9 is now replaced by L2 with a value of To Be Determined.

> 3. As it was already mentioned, GTP and GBP (top & bottom paste mask)
> files are most probably not needed. They are used to produce a stencil,
> that is used to apply solder paste to your board during automated
> assembly. Since you are going to solder it by hand, these files are
> redundant.

Who says I'm not going to reflow solder these boards? =)

I plan to order these boards from dirtypcbs.com - a stencil is $25 and would 
be cost efficient to use.

> 4. How difficult will it be to solder shielding without thermal
> relieves? They are causing artifacts around pads. When it happens, I
> usually either set thermal relief to full-contact or manually fill holes
> with small polygons (02.png)

The big red circle in 02.png is a bug, the others - I see your point and I 
hope I understand your proposed remediation. Aligned the vias better to get 
rid of the smallest gaps.

> 5. I see, that the width of 5V power trace is about 0.4 mm. I usually
> assume maximum current density for copper to be 10A per mm^2. There are
> different values on the internet, I'm using here what Russian PCB
> standards say. Assuming, that your outer layers will have 1 oz (35 um)
> copper, 150 mA requires 0.45 mm wide trace. Because of that I suggest
> making this trace thicker, maybe 1 mm or so. I also see, that the upper
> part of this trace is thicker, than the lower. It will be better to make
> the whole power trace of equal thickness (03.png)

Ok, made a 50 mil fat trace and tidied up the whole 3V3 LDO section.

> 
> 6. Some of RefDes are covering vias (04x.png)

Fixed.

> Anyways, the only critical issues, in my opinion, are R9 and thin trace
> carrying 5V power. 

Both should be addressed now.

> Other items are mostly cosmetic. I like your board.

Thanks! I'm ordering this board as it is now to put an end to the tweaking =).

/Fredrik
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