[Cryptech Tech] Novena dev-bridge board status

[Павел Шатов]

On 23.06.2015 22:20, Fredrik Thulin wrote:
> Jacob and Peter, thanks for all your comments. I'll try to respond to them all
> here.
>
> On Tuesday, June 23, 2015 10:28:36 AM Jacob wrote:
> ...
>> I spent some time going over the PDF schematic and Gerber files. Since
>> Eagle is not my preferred system, I am not fluent with it so up to now
>> I haven't looked at the source schematic and pcb under Eagle for these
>> latest files.
>>
>> I have some issues with the schematic and the layout. If it was my
>> board, I wouldn't feel comfortable to go to production at that stage.
>> Will it work if I go? it might, but I wouldn't bet on it.
>
> I wouldn't call this production, but of course I want the board to work so
> I've done what I can to address your issues.
>
> Jacob:
>> For example:
>> Schematic:
>> - R9 is 100 Ohm, meaning 50 mA max power to the design. The consumers on
>> the board, especially during switching, require more than that. The
>> board is probably starved.
>
> Right - that came with the copying of the significantly smaller novena entropy
> source board. As Peter said, figuring out the right value for R9 can be done
> later.
>
> Peter:
>> I took a closer look at the power supply inputs - it seems that the
>> Micro-USB VBUS is connected to VCC, meaning 3V3, which isn't right.
>
> No, it is connected to P-5.0V_MAIN. Added missing label in schematics to make
> that clear.
>
> Peter:
>> Suggest add schottky diodes, e.g. one BAT54C if 200mA is enough for
>> the board, between 5V/VBUS and U1:
>>
>> 5V ---|>|-+
>>            +-- U1 VIN
>> VBUS -|>|-+
>
> For protection against back currents? I already have the dual BAT54S in the
> BOM so that would be easy. I measure the STMF429 discovery board to around 190
> mA 5V, but it has that huge display to drive too... the 3V3 LDO is rated at
> 150 mA anyways (I have not added diodes yet).
>
> Jacob:
>> - Noise Generator: The shield is connected to AGND, but the analog
>> power supply (-15V) and the power amplifier are connected to digital
>> GND.
>
> DC charge pump is connected to GND yes - since it lives outside of the
> shielded area. Peter once said the charge pump could/should share GND with the
> noise generator circuit, but I'm a bit reluctant since I think it might
> introduce noise.
>
> The amplifier and digitizer on sheet 3 were mislabeled GND instead of AGND in
> the schematics. Fixed.
>
> Jacob:
>> Also, I could not find AGND return in the schematic.
>
> I think I'll blame Eagle there. The only way I found to get a good solid
> connection between GND and AGND (in the one place where they are tied together
> at the boundary underneath the shield) was to make it with polygons of equal
> rank that overlaps. Polygons are just shapes on the board and not represented
> in the schematics, but I'll make a note of this on sheet 3.
>
> Jacob:
>> Also, the designed analog plane under the noise sub-system is supposed
>> to be decoupled from the digital ground. However the digital ground and
>> the digital power are extended under the whole region, coupling unwanted
>> noise to the expected analog plane.
>
> Better now? Removed POWER plane underneath the shield. AGND has a polygon on
> GND layer (15) and also on bottom layer. The latter is just to make it
> visible. I'll confess to not really knowing what I'm doing with these separate
> ground planes - just making what I believe are good guesses.
>
> Jacob:
>> - I don't see the Ref Des of the decoupling caps of the STM32F in the
>> PDF, so it is hard for me to verify association to the layout
>> ( I suspect that their placement on board is not optimal).
> ...
>> I opened up the schematic in Eagle to identify the
>> caps, so for example please look at C17 and C33. C17 is a bulk
>> capacitor, - can be away from the chip. C33 is 0.1uF and needs to be
>> close to the relevant pin and if more than 2mm away then it should have
>> good vias to the planes.
>> However, in the layout (see attached pic) C17 is near the processor pin
>> while C33 is too far away (yellow path in pic) and without low impedance
>> path to the power plane. The two caps need to be switched around, and
>> the bulk cap C17 needs to have good size vias to the planes (to GND
>> *AND* to PWR)
>
> Thanks for pointing that out. I swapped C17 and C33 locations and generally
> did what I could to minimize the distances between pins and caps. Keeping it
> under 2 mm is a real challenge when the board is 1.2 or 1.6 mm thick, for
> bypass capacitors on the bottom side.
>
> What is a good sized via here?
>
> Jacob:
>> If the missing RefDes just a PDF issue or also in the source schematic?
>> - there might be other issues - I haven't gone over all sections yet.
>
> Restored the RefDes:es in the schematics.
>
> Attaching new set of files.
>
> /Fredrik
>
>

Fredrik, I've taken a look too. My thoughts are below.

1. It is usually recommended to completely fill internal power/ground 
layers with polygons. It improves manufacturability of the board, 
because it will have constant thickness and will be less susceptible to 
delamination. I suggest filling empty space in the upper-left corner of 
internal power layer with small ground polygon (01.png)

2. I don't understand R9. RC filters must not be used to filter power 
rails, because you are effectively inserting a resistor in series with 
load, which causes voltage drop. Power rails must be filtered with LC 
filters. Instead of R9 an inductor can be used, or a ferrite bead maybe.

3. As it was already mentioned, GTP and GBP (top & bottom paste mask) 
files are most probably not needed. They are used to produce a stencil, 
that is used to apply solder paste to your board during automated 
assembly. Since you are going to solder it by hand, these files are 
redundant.

4. How difficult will it be to solder shielding without thermal 
relieves? They are causing artifacts around pads. When it happens, I 
usually either set thermal relief to full-contact or manually fill holes 
with small polygons (02.png)

5. I see, that the width of 5V power trace is about 0.4 mm. I usually 
assume maximum current density for copper to be 10A per mm^2. There are 
different values on the internet, I'm using here what Russian PCB 
standards say. Assuming, that your outer layers will have 1 oz (35 um) 
copper, 150 mA requires 0.45 mm wide trace. Because of that I suggest 
making this trace thicker, maybe 1 mm or so. I also see, that the upper 
part of this trace is thicker, than the lower. It will be better to make 
the whole power trace of equal thickness (03.png)

6. Some of RefDes are covering vias (04x.png)

Anyways, the only critical issues, in my opinion, are R9 and thin trace 
carrying 5V power. Other items are mostly cosmetic. I like your board.

--
With best regards,
Pavel Shatov
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