[Cryptech Tech] Novena dev-bridge board status

[Peter Stuge]

Jacob wrote:
> Peter, when I talked about my "suspicion" re decaps placement, I tried to 
> be gentle :-).

I for one prefer direct but this is tricky - everyone is different. :)


> I opened up the schematic in Eagle to identify the caps, so 
> for example please look at C17 and C33. C17 is a bulk capacitor, - can be 
> away from the chip. C33 is 0.1uF and needs to be close to the relevant pin 
> and if more than 2mm away then it should have good vias to the planes.
> However, in the layout (see attached pic) C17 is near the processor pin 
> while C33 is too far away (yellow path in pic) and without low impedance 
> path to the power plane. The two caps need to be switched around, and the 
> bulk cap C17 needs to have good size vias to the planes (to GND *AND* to 
> PWR)

Yep, I agree that it would be better. I guess that it isn't critical.


> I have a high respect for Lee Richie (the book author, although I'm not 
> familiar with John Zasio, who wrote the relevant Power Section), but I 
> don't agree with the statement that decap placement is immaterial if 
> you have a very good connection decap-to-plane:

Right, I know that it's quite a controversial statement. :)


> a. Planes are not ideal (unlike his test board) - they are like Swiss 
> cheese with all the vias holes, thus having noticeable inductance.
> Also, he uses 3 mil dielectric thickness to get good plane coupling -
> state of the art for normal fab runs even today.

Yes, that's true. Our board has not been designed to have optimal planes.


> b. His calculations are overly simplistic. They may work at fairly low 
> frequency (book is written in 2003, updated in 2008), but if you look at 
> the decaps recommendations of the major FPGA companies today, you would
> see how much they stress a good decap placement regimen.

I see the book as explaining very well why things work even when one
might expect them not to, rather than an excuse to make compromises
where it isn't really neccessary.


> c. My Power Integrity simulations I ran in the past, corroborated by 
> experts in the field, did show a marked plane impedance changes as a 
> function of decap placement.

Very interesting! Would you go so far as to say that your simulation
results disagree with the measurement results in the book? I'd love
to learn more!


Thanks

//Peter