[Cryptech Tech] Novena dev-bridge board status

[Jacob]

On 6/23/2015 12:46 PM, Peter Stuge wrote:
> Jacob wrote:

>
>> - I don't see the Ref Des of the decoupling caps of the STM32F in the PDF,
>> so it is hard for me to verify association to the layout
>> ( I suspect that their placement on board is not optimal).
>
> Recommend the "Right The First Time" book that was posted already.
> Quoting chapter 35 Power Subsystem Inductance:
> --8<--
> Capacitor Placement
>
> Because of the low inductance of the power plane pair, the placement
> of the capacitors is not as critical as the consideration of via
> length and using the power plane close to the IC package side of the
> PC board.
>
> To show the effect of capacitor placement, a single 0.1 µF 0603
> capacitor was meassured on four different locations on the PCB, as
> depicted in Figure 35.9. The two coax measurement leads were on one
> of the narrow ends of the board. [10.3" x 4.0" in size] The capacitor
> locations were at approximately 2.5" intervals down the long
> dimension of the board. Figure 35.10 shows a magnified view of the
> impedance vs. capacitor placement.
>
> Notice that the variation of the placement of the capacitor has only
> an 8% change in the series resonance frequency and almost no change
> in the parallel resonance frequency. The effects of the copper plane
> resistance seem to be larger than the inductive effects.
> -->8--
>
> The book recommends designing power planes to function as capacitance,
> rather than to rely on discrete capacitors, making for a much more
> robust design.
>
> Shorter traces are of course still always better.
>
>
> //Peter

Peter, when I talked about my "suspicion" re decaps placement, I tried 
to be gentle :-). I opened up the schematic in Eagle to identify the 
caps, so for example please look at C17 and C33. C17 is a bulk 
capacitor, - can be away from the chip. C33 is 0.1uF and needs to be 
close to the relevant pin and if more than 2mm away then it should have 
good vias to the planes.
However, in the layout (see attached pic) C17 is near the processor pin 
while C33 is too far away (yellow path in pic) and without low impedance 
path to the power plane. The two caps need to be switched around, and 
the bulk cap C17 needs to have good size vias to the planes (to GND 
*AND* to PWR)


Now, regarding your reference to the book:

I have a high respect for Lee Richie (the book author, although I'm not 
familiar with John Zasio, who wrote the relevant Power Section), but I 
don't agree with the statement that decap placement is immaterial if you 
have a very good connection decap-to-plane:
a. Planes are not ideal (unlike his test board) - they are like Swiss 
cheese with all the vias holes, thus having noticeable inductance.
Also, he uses 3 mil dielectric thickness to get good plane coupling - 
state of the art for normal fab runs even today.
b. His calculations are overly simplistic. They may work at fairly low 
frequency (book is written in 2003, updated in 2008), but if you look at 
the decaps recommendations of the major FPGA companies today, you would 
see how much they stress a good decap placement regimen.
c. My Power Integrity simulations I ran in the past, corroborated by 
experts in the field, did show a marked plane impedance changes as a 
function of decap placement.



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