[Cryptech Tech] Novena dev-bridge board status

[Jacob]

On 6/23/2015 1:33 AM, Fredrik Thulin wrote:
> After a couple of long days I've put together what I believe is the dev-bridge
> board I will produce (unless someone takes a look and shouts out really
> quickly about issues).
>
> Pavel has reviewed the schematics for the FMC interface and the STM32
> configuration. There is an entropy source circuit present, but not connected
> to the same FPGA pin as before (new pin is F_DX18).
>
.
.
.
> I hope I got Gerber creation right for 4 layer board. The inner copper looks
> plausible to me in terms of connecting with the right vias and not connecting
> with the other vias. Please let me know quickly if I did not =). Hoping to
> order tomorrow, after having looked things over with less sleepy eyes.
>
> /Fredrik

I spent some time going over the PDF schematic and Gerber files. Since 
Eagle is not my preferred system, I am not fluent with it so up to now 
I haven't looked at the source schematic and pcb under Eagle for these 
latest files.

I have some issues with the schematic and the layout. If it was my 
board, I wouldn't feel comfortable to go to production at that stage. 
Will it work if I go? it might, but I wouldn't bet on it.

For example:
Schematic:
- R9 is 100 Ohm, meaning 50 mA max power to the design. The consumers on 
the board, especially during switching, require more than that. The 
board is probably starved.
- Noise Generator: The shield is connected to AGND, but the analog 
power supply (-15V) and the power amplifier are connected to digital 
GND. Also, I could not find AGND return in the schematic.
Also, the designed analog plane under the noise sub-system is supposed 
to be decoupled from the digital ground. However the digital ground and 
the digital power are extended under the whole region, coupling unwanted 
noise to the expected analog plane.
- I don't see the Ref Des of the decoupling caps of the STM32F in the 
PDF, so it is hard for me to verify association to the layout
( I suspect that their placement on board is not optimal).
If the missing RefDes just a PDF issue or also in the source schematic?
- there might be other issues - I haven't gone over all sections yet.

Layout:
Various small issues, but don't have the time to analyze them all at the 
moment. No show stopper though so far, except maybe decoupling 
capacitors placements and noisy digital planes under the noise generator.

Jacob



I just touched on the surface