[Cryptech Tech] core configuration

[Peter Stuge]

Paul Selkirk wrote:
> The biggest disadvantage is additional complexity on the software side.
> Each app would have to probe the FPGA for its installed cores.

I don't know that this is in fact a disadvantage.


> And since the base address of each core is no longer at a fixed
> location, the app would have to add the base address to the
> register address on each read or write.

I think it's good that cores are self-describing, and specify their
register window sizes.

To make (both hardware and software) debugging easier I would suggest
to force base addresses to be 4k- or 64k-aligned.


//Peter