[Cryptech Tech] core configuration

[Basil Dolmatov]

Support this approach strongly. 

dol@ с iPad

> 10 июня 2015 г., в 20:28, Paul Selkirk <paul at psgd.org> написал(а):
> 
> I've been toying with the idea of dynamically generating the core
> configuration for the FPGA. What I've come up with is a python script
> that takes a list of cores (from the command line or a config file), and
> generates a core_selector.v file, which instantiates the cores and
> provides the read/write addressing. This replaces the hierarchical set
> of selectors in core/platform/common/core_selector.
> 
> The biggest advantage of this is that it would allow multiple instances
> of cores. So e.g. an HSM might have a pool of signers, rather than a
> single signer. This just wasn't possible with the fixed-address scheme.
> 
> It also simplifies the bitstream build slightly, and removes the need
> for the entire core/platform/common repo. We could even potentially
> reduce the number of address lines we need, since the cores would
> contiguous, rather than in a sparse array.
> 
> The biggest disadvantage is additional complexity on the software side.
> Each app would have to probe the FPGA for its installed cores. (Granted,
> they currently do this by probing fixed addresses for name/version
> strings.) And since the base address of each core is no longer at a
> fixed location, the app would have to add the base address to the
> register address on each read or write.
> 
> This can all be found in the 'config_core_selector' branch on the
> following repos:
> core/platform/novena (add config/, change sw/*)
> core/comm/eim (change comm_regs sys_rst to reset_n for consistency)
> core/math/modexp$ (12 bits address -> 8, for now)
> core/rng/trng (make cores contiguous, add mixer name/version)
> 
>                paul
> _______________________________________________
> Tech mailing list
> Tech at cryptech.is
> https://lists.cryptech.is/listinfo/tech