[Cryptech Tech] Short note on the current FPGA activities

[Joachim Strömbergson]

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Aloha!

Шатов Павел wrote:
> I believe I'll complete my small sub-plan to develop what you call a
> baseline project in a week. Adding SHA-1 core to it should take
> another week or two.

(A week or two for connecting SHA-1 sound very much. We are not going to
reimplement it.) If the bram, adder-test HW clocked using system_clk
from CLK2 it should be a snap to integrate SHA-1. Paul has written C
test code that we should be able to use.

> Let's do it like this. If you don't have any objections, I'll finish
> my baseline project and send it to you for a review and testing next
> week. After we make sure that we have a stable working baseline we'll
> start adding cores to it.

And just to check what we are talking about. That baseline would include:

(1) novena_fpga top level containing tthree submodules:

(I) Complete EIM interface in a submodule including all clock
implementation (PLL, DCMs etc as neededed) with bclk at 133 MHz. The
internal interface is a memory like interface like this:

      output wire          clk133,
      output wire          cs,
      output wire          we,
      output wire [xy : 0] address,
      output wire [31 : 0] write_data,
      input  wire [31 : 0] read_data,

This interface would be running at 133 MHz in phase with bclk (it would
be bclk)


(II) A cryptech_system module that accepts an interface like the one
from EIM (switch input/output) and also the system_clk and reset. This
module would contain a submoudle that implements the clock domain
crossing logic (built using fifos). It would also contain an example
design - bram + simple adder logic.

(III) A module that implements the reset and clocking needed. Basically
the module I have today in my baseline. The clk50 would be connected to
system_clk in (II).


(2) fpga_setup (I prefer eim_setup because that is what the code does,
but what the heck.) SW. Sound great that you have a clean version of this.

(3) Simple test SW that uses the bram and adder logic and hopefully
don't bump into any read/write errors.


Does this match what you are proposing? If so, yes I would very much
have that done. Having it next week would be great!

With best regards
JoachimS

- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
========================================================================
 Joachim Strömbergson          Secworks AB          joachim at secworks.se
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