[Cryptech Tech] EIM Problems
Joachim Strömbergson
joachim at secworks.se
Sun Jan 4 21:53:06 UTC 2015
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Aloha!
Leif Johansson wrote:
> Re-reading this thread (as a naive on-looker) I can't figure out
> what you guys are saying - if this is a design choice in the novena
> then its just a matter of "gilla läget" [1] or am I missing
> something?
As far as I see it (see other, a bit longer mail.) As Randy suggested
(and I agree with) in an earlier mail we, should give Bunnie credit for
getting working FPGA designs that communicates with the CPU via the EIM.
The Freescale documentation states a different clock frequency max than
what Bunnie is using (104 vs 133). But after testing I believe more in
what Bunnie does than what Freescale writes. One thing to note is that
Freescale (as far as I am able to search) does not actually provide the
documentation for the exact version of the CPU used on the real Novena,
but only for parts with 1 GHz clock. If that has anything to do with the
EIM clock I don't know (I can't find the specific clock source for the
EIM_BCLK in the documentation.)
So yes, we need to "gilla läget" and design for what is really there.
And I lean towards Bunnies definition of what is there.
Does this makes it more understandable?
And also let me state that I really appreciate that Paul Shatov clearly
read the documentation firmly and found this discrepancy. We need more
good eyes and minds.
- --
Med vänlig hälsning, Yours
Joachim Strömbergson - Alltid i harmonisk svängning.
========================================================================
Joachim Strömbergson Secworks AB joachim at secworks.se
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