[Cryptech Tech] FMC Arbiter

[Павел Шатов]

Hello!

I uploaded initial version of FMC interface arbiter for Novena and 
corresponding demo program for the dev-bridge board:
/user/shatov/fmc-test
/user/shatov/novena-fmc-arbiter

It would be great, if someone else could test them on his set of boards.

Speaking of hardware issues, I got the following:

1) One of the expansion connector pins was not soldered well (see 
attached photo), as a result, one of the address lines was always read 
as 0 by the FPGA. In case you observe bits stuck at 0, inspect expansion 
connector for bad solder joints.

2) Expansion connector turns out to be very sensitive to misalignment. 
Sometimes the demo program starts getting readback mismatch errors, that 
are all in the same bit. After I gently push the bridge board to align 
it in parallel with the base, everything starts working fine again. I 
also think, that such connectors are rated for a limited number of 
mating cycles, so I try not to separate the boards without reason.

3) My Novena somehow doesn't work properly, when bridge board is powered 
from it. I removed diode D2 and added solder bridge instead to power my 
bridge board from wall Micro-USB phone charger.

4) 25 MHz HSE crystal on my board doesn't work, that's why I temporarily 
configured it to operate from 16 MHz HSI oscillator. Fredrik gave me a 
hint on how to fix this, but I haven't time to get to an RLC meter so far.

FMC arbiter is a bit different from EIM arbiter:

1) Width of address bus is parametrized (bridge board has 22 lines). 
This way we won't have to find and replace all occurences of [21:0] in 
Verilog code, when time comes to adapt the code for Alpha board.

2) Clock manager no longer uses an IP core to synthesize system clock 
frequency, it now instantiates DCM_SP primitive directly. This should 
save Paul from messing with CoreGen during bitstream generation. System 
frequency can be changed by changing multiply and divide factors during 
instantiation of clock manager module.

FPGA firmware has one 32-bit test register instead of core selector, it 
can be used to write something to FPGA and then read it back. Both data 
and address buses can be tested, read comments in novena_fmc_top.v for 
more information.

Demo program for STM32 keeps writing "random" stuff in FPGA, reading it 
back and comparing. As long as everything is fine, green LED should be 
on and yellow LED will blink after every batch of tests. In case of 
readback mismatch, red LED will be turned on.

--
With best regards,
Pavel Shatov
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