[Cryptech Tech] status alpha board designers

[Jacob]

> Jacob, we understand, that Alpha board is going to be complex, that's
> why we want to reuse as much as possible. One of ways forward we are
> considering, is using this CPU+RAM module: http://www.imx6rex.com/
> Could you please have a look at it? The only problem with this module,
> is that it has lots of unnecessary interfaces (audio, video, ethernet,
> etc) and doesn't have EIM. I think, that it will be easy to adapt this
> module to our needs by removing unneeded signal traces and then routing
> EIM signals instead. Is this possible? I can provide detailed list of
> CPU pins, that we don't need, along with a list of new pins, that should
> be exposed from this module.

I looked at the REX module design. It is a very dense board (with 
blind/buried vias). to reuse it while adding EIM lines would not be easy:
- need to add a connector (the pins that would be freed after doing away 
with the audio-visual and ethernet functionality are not enough for the 
added ADDR/DATA lines required for the EIM: 24 ADDR + 32 DATA + 10 or so 
CTRL).
- The routing is very dense and sensitive: tight timing/length 
requirements, many controlled impedance traces, large number of very 
dense decoupling capacitors under the BGA. Disruption of these is not 
pretty, and due to the many added EIM lines a big chunk of the board 
would have to be re-routed and re-analyzed for SI (a somewhat mitigating 
factor would be if all the EIM pins would come out from the opposite 
quadrants of the BGA relative to the DDR3 pins).
- Interesting to note that the schematic does not show termination 
resistors on the DDR3 lines. I did not check if the iMX6 has internal 
terminations or not, but usually external resistors provide much greater 
signal tuning capabilities.
Certainly you would have to add termination resistors for all EIM's ADDR 
and DATA lines to minimize reflection due to the distance going to a 
separate FPGA board.

I would venture to say that reusing the REX module would maybe save 
10-25% max time compared to layout from scratch (doing from scratch 
would make it less dense - we have the area. I was told that 75X130mm 
board (with PS + FPGA + Connectors) would be a good target, and this is 
doable with single board design).
Another issue on the plate - reusing the board would probably require 
the use of Altium (used to layout the board) which is not the best for 
this complex work.

> Could you please give us an estimate of how long it will take to modify
> that module and then design FPGA-based carrier board for it?
 > Maybe we can make Alpha two-board, and once it's ready, we will start
> working towards single-board Beta.

I need to think a bit about this, but based on my arguments above I am 
hesitant to recommend a REX module re-use.

Jacob