[Cryptech Tech] status alpha board designers

[Jacob]

> What seems clear is that we need to get a much more complete schematic done
> first.

Is there a writeup that shows the expected crypto ops throughput rate of 
the alpha board? Is there an arbiter in the uC that prioritizes requests 
to the FPGA?

--- thinking aloud ---
Since the FPGA is not connected to an external memory, I surmise that 
all  requests are queued at the uC and then scheduled along the 66MHz 
bus to the FPGA after the latter finishes each crypto op processing.
This may be OK since the I/F to the board is through a relatively slow 
PKCS#11 protocol - hence low request rates - and not through a network 
connection.

Also, is a graceful restart necessary (maybe already designed in?) to 
reschedule users' crypto ops requests in the queue after a possible 
board power failure?
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Jacob