[Cryptech Tech] reverse engineered bitstream for a FPGA

[Bernd Paysan]

Am Montag, 13. April 2015, 19:45:54 schrieb Rob Austein:
> At Tue, 14 Apr 2015 02:20:18 +0300, ????? ????? wrote:
> > Is this good news or bad news? :)
> 
> Good news, I think: opacity of bitstream generation tools is a serious
> problem, so anything that makes it easier to check whether the
> generated bitstream has any relationship to the input Verilog is
> probably a good thing.

If you can extract the LE configuration + routing info from the bitstring and 
convert it into Verilog, you could do a formal verification if the bitstring 
matches your design.

-- 
Bernd Paysan
"If you want it done right, you have to do it yourself"
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