[Cryptech Tech] Some measurement results for FPGA with avalanche entropy source

[Fredrik Thulin]

On Saturday, September 06, 2014 04:10:05 PM Randy Bush wrote:
...
> > (2) Getting a fairly good looking avalanche noise tightly integrated
> > onto Novena. There exists a pluggable I/O board for Novena and Paul
> > would look into getting those for us. If we don't have one of those,
> > we need to look at some of the other interfaces as options.
> 
> my memory is that bunnie said november.  likely we can beg one or two in
> the interim.
> 
> > Also, both the board from Benedict and Fredrik can't just be stacked
> > on top of a header, but connect with wires. I would love to have a
> > small board with the noise source just to push down on headers to make
> > a single integrated unit.
> 
> a bit close for ches, but perhaps an ietf goal?

This is how my current prototype (rev06) looks fitted on the GPIO header of a 
Raspberry Pi. Having a similar add-on for the Terasic DE0-board before Ches is 
doable. I believe we don't know how the connectors on the Novena I/O board 
looks like yet so that won't be possible.

The transistor (noise source) and all the jumpers can be put on the bottom 
side as well, leaving only the blinkenlights on top.

/Fredrik
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