[Cryptech Tech] Some measurement results for FPGA with avalanche entropy source

[Randy Bush]

> (1) Getting Cryptech FPGA HW up and running on Novena. Paul is basically
> there. But we need to be able to replicate easily. And also using I2C
> interface would make the RNG less impressive and harder to extract
> enough data to run Dieharder (preferably being able to do so as a demo
> on site). So we need:
> 
> - Adaptation to use EIM
> - Documentation to get HW design into FPGA + SW to actually send
>   commands via EIM to read data in the FPGA

and whatever we need to get all of us at current sobs rev level etc.

> (2) Getting a fairly good looking avalanche noise tightly integrated
> onto Novena. There exists a pluggable I/O board for Novena and Paul
> would look into getting those for us. If we don't have one of those,
> we need to look at some of the other interfaces as options.

my memory is that bunnie said november.  likely we can beg one or two in
the interim.

> Also, both the board from Benedict and Fredrik can't just be stacked
> on top of a header, but connect with wires. I would love to have a
> small board with the noise source just to push down on headers to make
> a single integrated unit.

a bit close for ches, but perhaps an ietf goal?

> (3) Complete the RNG HW chain. The major blocks (SHA-512 and ChaCha)
> are in the repo. I've started working on putting together the state
> machines and API needed to control the RNG. And building a test bench
> for the chain. This is actually the easiest part imho.

you would say so :)

> (1) and esp (2) is what I see takes longest time to do.

yep

> I actually considered building the complete RNG onto the TeasIC
> DE0-board just to show how compact it can be. But the Novena running
> Dieharder is a much better Dog & Pony platform.

agree.  terasic is nice in the lab, exposes more.  but for us software
types, having the fpga close to a usable operating system is much more
understandable.

randy