[Cryptech Tech] Open JavaCard platform

[Vicente Sanchez-Leighton]

Hello Joachim, hello everybody.

Joachim Strömbergson wrote :
> AFAIK there are no open ARM implementations. The one I know, a student
> project in Sweden was killed off by ARM pretty fast. There are a few
> MIPS ones also. Don't know their implementation status.
I don't know either about any open ARM implementations. On Leon and IA32
there's a partially open-source hypervisor called xtratum
(http://www.xtratum.org/, http://www.fentiss.com/). On MIPS there are
open implementations (at least of older architectures), but not -yet-
open hypervisors.

Joachim Strömbergson wrote:
> IMHO should not force their users into a given architecture but be as
> open as possible in terms of technology. What we need to do is decide on
> bit and byte ordering, data bus widths etc. But those can always be
> fixed with simple HW converter. For the reference/example designs we
> will be using specific cores or companion MCUs (which could be an ARM
> Cortex something). But if a user wants to use OpenRISC, Microblaze, a
> hard ARM core, MIPS or x86 in a separate CPU that should all be possible.
>
> Currently I'm not following any specific bus standard, but is pretty
> close to WISHBONE, APB, CoreConnect - It is basically the interface for
> a memory with 32-bit wide MSB data.
My domain is more hypervisors, TEEs and OSes and not hardware design, so
bear with me: I would feel some kind of bus mechanism for -at least-
memory protection or -better- IOMMU would be a must in such an
architecture as cryptech, to protect functions of different security
levels from each other. In the ARM architecture there's a 33rd lane in
the bus to signal to all coprocessors and memory if the system is
running in normal or secure mode (TrustZone). A full fledged IOMMU
scheme would be better, but you might feel it is too much of a
constraint for the cryptech user-designers.

-- 
Vicente Sanchez-Leighton, mail: vsanchezleighton at gmail.com


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