[Cryptech Tech] SHA-256 has been added to the cryptech repo.
Basil Dolmatov
dol at reedcat.net
Tue Feb 25 05:06:33 UTC 2014
19 февр. 2014 г., в 18:17, Joachim Strömbergson <joachim at secworks.se> написал(а):
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA256
>
> Aloha!
>
> The first HW core has now been added to the Cryptech repo.
>
> core/sha256 is an implementation of SHA-256 that is fairly compact
> iterative with one cycle/round. The W scheduling is done in parallel
> which makes the init phase short.
>
> There are testbenches for the sub modules, the core as well as the two
> wrappers. sha256.v is a wrapper with a simple memory like interface and
> wb_sha256.v is a Wishbone interface.
>
> Implementation wise the core is less that 10 kLEs and 3500 registers in
> Altera Cyclone IV GX. It can be clocked in excess of 70 MHz which means
> that it can process more than 64 MByte/s.
>
> The status of the core is that it is (read: should be) done. The core
> simulates correctly and has been implemented in HW in Altera devices.
> However I have not implemented it in Xilinx devices and with the Xilinx
> tool chain yet.
>
>
iMac-dol:toolruns dol$ make all
iverilog -o wb.sim ../src/tb/tb_wb_sha256.v ../src/rtl/wb_sha256.v ../src/rtl/sha256_core.v ../src/rtl/sha256_k_constants.v ../src/rtl/sha256_w_mem.v
../src/tb/tb_wb_sha256.v:164: warning: task definition for "dump_dut_state" has an empty port declaration list!
../src/tb/tb_wb_sha256.v:208: warning: task definition for "reset_dut" has an empty port declaration list!
../src/tb/tb_wb_sha256.v:224: warning: task definition for "init_sim" has an empty port declaration list!
../src/tb/tb_wb_sha256.v:245: warning: task definition for "display_test_result" has an empty port declaration list!
../src/tb/tb_wb_sha256.v:270: warning: task definition for "wait_ready" has an empty port declaration list!
../src/tb/tb_wb_sha256.v:364: warning: task definition for "check_name_version" has an empty port declaration list!
../src/tb/tb_wb_sha256.v:392: warning: task definition for "read_digest" has an empty port declaration list!
../src/tb/tb_wb_sha256.v:420: syntax error
Assertion failed: (current_task == 0), function VLparse, file parse.y, line 2367.
sh: line 1: 19476 Done /usr/local/iverilog/lib/ivl/ivlpp -L -F"/var/folders/pr/_xwtqbbn7dv21n82vlxxsq040000gn/T//ivrlg2138231be" -f"/var/folders/pr/_xwtqbbn7dv21n82vlxxsq040000gn/T//ivrlg138231be" -p"/var/folders/pr/_xwtqbbn7dv21n82vlxxsq040000gn/T//ivrli138231be"
19477 Abort trap: 6 | /usr/local/iverilog/lib/ivl/ivl -C"/var/folders/pr/_xwtqbbn7dv21n82vlxxsq040000gn/T//ivrlh138231be" -C"/usr/local/iverilog/lib/ivl/vvp.conf" -- -
make: *** [wb] Error 134
M?
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