[Cryptech Tech] SHA-256 has been added to the cryptech repo.

[Joachim Strömbergson]

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Aloha!

The first HW core has now been added to the Cryptech repo.

core/sha256 is an implementation of SHA-256 that is fairly compact
iterative with one cycle/round. The W scheduling is done in parallel
which makes the init phase short.

There are testbenches for the sub modules, the core as well as the two
wrappers. sha256.v is a wrapper with a simple memory like interface and
wb_sha256.v is a Wishbone interface.

Implementation wise the core is less that 10 kLEs and 3500 registers in
Altera Cyclone IV GX. It can be clocked in excess of 70 MHz which means
that it can process more than 64 MByte/s.

The status of the core is that it is (read: should be) done. The core
simulates correctly and has been implemented in HW in Altera devices.
However I have not implemented it in Xilinx devices and with the Xilinx
tool chain yet.

If someone wants to contribute there are several things that can be done
that I would appreciate:

* Add more test cases for simulation.
* Compile and simulate using Modelsim or any other simulator
* Build using Xilinx toolchain or any other FPGA/ASIC toolchain
* Browse/read the code and give feedback.

My next activity for the core is to test it extensively in real FPGA
hardware as soon as the coretest core framework has been completed.
Currently I'm debugging the host interface for coretest.

Unless someone else wants to I will also write a design spec/brief that
will be included in the core repo.

- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
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 Joachim Strömbergson          Secworks AB          joachim at secworks.se
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