[Cryptech Tech] ASIC implementation page on wiki

[Joachim Strömbergson]

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Aloha!

Bernd Paysan wrote:
> Some comments:
> 
> * Memories - in an FPGA design, you can let the synthesis tool choose
> your memory blocks from an RTL description - and that's the right way
> to do.  ASIC process flows don't work that way (they don't choose
> memory blocks).  Good design is to wrap the memory up in one Verilog
> module, so you can replace that for the ASIC design.

Actually, modern ASIC synthesis tools will be able to automatically
generate simpler memories. But that is nitpicking. Normally you will use
a dedicated memory compiler and then instantiate the macro from the chip
specific library. In any case having the memories in separate moduls is
a good design rule and that is how I do it. I will update the text to
clarify this.


> * Synchronous/asynchronous reset: Both Altera and Xilinx flip-flops
> offer asynchronous reset.  Use it.  It will help porting to an ASIC.
> You might want to gate your clock with the reset so that reset
> edge/clock edge timing problems disappear.  In an ASIC you implement
> a clock driver which starts after the reset goes away - problem
> solved.

Actually it isn't that clear cut. Xilinx actively recommends against
using asynch reset, see:

http://www.xilinx.com/support/documentation/white_papers/wp231.pdf
"Avoid asynchronous reset because it prevents packing of registers into
dedicated resources and affects performance, utilization, and tool
optimizations."

On the other hand Xilinx in a later WP even recommends not implementing
any dedicated reset at all since they will reset all registers as part
of the configuration:

http://www.xilinx.com/support/documentation/white_papers/wp272.pdf.

In Altera devices the same recommendation (not specifying reset state
for registers) leads to a bigger design. And for Altera the availability
of asynch support differs between generations. The later devices with
LABs have dedicated labclr control signals that support asynch reset.
For older devices Altera has been recommending synchronous reset. Their
updated recommendations is to use Synchronous Asynchronous Reset:

http://www.altera.com/literature/hb/qts/qts_qii51006.pdf

I agree however that for ASIC design it is way more common to use asynch
reset (though I have been working on a few ASIC where synch reset is
used.) And the specific reset strategy is always implemented in a
dedicated block which feeds its own network.

I will update the text and consider what we want to use in the FPGA
desgin. Since all registers are always in a separate process
(reg_update) in each module it is fairly easy to change the strategy.


> * Avalanche diode noise: Depending on the process options, it might
> be possible to have an internal avalanche diode.  This sort of diodes
> are often part of the ESD structures in IO pins, so with some
> knowledge of the process, you just can use that.  In a power
> management capable process, you can also include the stuff for the
> step-up converter (excluding coils and capacitors, of course).

Good point. Being able to add more internal noise sources make an ASIC
better. This does not mean that an external source must be removed. The
more the merrier.


> * Ring oscillator: I'm pretty sure the adder-based ring oscillator
> will produce a working oscillator on an ASIC, with somewhat similar
> noise characteristics, as the carry chain in the FPGA is just a
> "hardcoded" carry chain, i.e. about the same thing you would do in an
> ASIC.  Of course, the resulting circuit has to be characterized, and
> hand-layouted ring oscillators can do better (and a lot smaller - a
> few inverters instead of several full adders).

Yes. I think that is what is said in the text already, but will update
to clarify.


> * Get Cadence/Synopsys to sponsor the tools for that project
> 
> * Cooperate with a fab with design center services (those do have the
> tools available)
> 
> * Cooperate with an university which has the tools and connections to
> fabs.

True all of them, and Europractice might be the best way forward in
terms of openness. At least if we want to do a Cryptech ASIC as part of
an open research project.

http://www.europractice-ic.com/


> Having worked in the semiconductor industry for quite some time, the
> best contact I have is to TowerJazz, with one of my former bosses
> ending up as the European sales director there.

Good to know. I have worked with Samsung, IBM, LSI, TSMC, UMC, SMIC, NEC
and ST as fabs for the chips I've been involved in and have a fairly
good network. But close contacts is always good.


- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
========================================================================
 Joachim Strömbergson          Secworks AB          joachim at secworks.se
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