[Cryptech Tech] Roadmap & remarks about the opportunity of developing a secure TOR router on the Novena platform.

[Joachim Strömbergson]

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Aloha!

Good that you are not designing a CPU from scratch. OpenRISC is at
available and have good support of tools and has been proven in many
FPGA and ASIC designs.

★ STMAN ★ wrote:
> Building a TOR processor, a non-micro-coded processor, a pure hard 
> coded logic controller, is from far the best approach to reduce the 
> attack surface to the minimum level.

Sorry, you lost me there, can you elaborate?

And I think we are still talking about different types of systems here.

The minimal move-the-key-handling-to-a-separate-machine that I talked
with Linus about should definitely only require a very simple, hard
coded FSM.

A full router would require at least a core do do control plane
processing. But then I get confused with the talk about PCIe and having
a board inside a PC.

Can we start by discussing what basic functions you see need to be
supported and the performance targets?

- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
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 Joachim Strömbergson          Secworks AB          joachim at secworks.se
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