[Cryptech Tech] Roadmap & remarks about the opportunity of developing a secure TOR router on the Novena platform.

[Joachim Strömbergson]

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Aloha!

★ STMAN ★ wrote:
> No, of course, I don’t trust Xilinx implementation of PCIe as it is 
> impossible to check the corresponding VHDL code. Now, there are many 
> « Free VHDL PCIe cores » available on OpenCore.

Have you tried them? Most of them are bridges and not complete PCIe. And
few of them are proven in real devices. Is my experience.

> But in the project we want to develop, this may not be such a big 
> problem : The workaround would be to cipher all the messages we 
> exchange on the PCIe bus.
> 
> And in the particular project we are planing : It would mean using 
> the PCIe bus to exchange TCP/IP paquets with the Secure TOR router : 
> - We would have a driver on the PC hooking TCP/IP stack packets to 
> encrypt and send them to the PCIe TOR Router end-point, so if the 
> PCIe has some backdoors, as we would cipher the data sent through
> it, these backdoors would be useless.
> 
> Do you agree with this approach ?

Yes, that might work, but it looks kludgy to me. I would rather build a
system with either a separate MCU for control or an internal core in the
FPGA doing the routing and then have a simpler, low latency interface
between the cores. PCIe is complex and will eat a lot of resources in
the FPGA.

If you really are thinking of going that direction, you might want to
look at the NetFPGAs:

http://netfpga.org/

- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
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 Joachim Strömbergson          Secworks AB          joachim at secworks.se
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