[Cryptech Tech] Work package suggestion: Cryptech on Novena

[Randy Bush]

>> are transactions synchronous, or queueable.  the latter is very
>> complex.
> I think that from the start they are synchronous. But having fifos
> would probably make for better performance without adding too much
> complexity.

sorry, i should have s/queueable/asynchronous/.  queues can be dealt
with one entry at a time to be synch.

>> does the fpga have access to green ram?  read-only or rw?  i.e. can
>> we do a ring buffer of commands packed into tlvs, each possibly
>> pointing to data (as one does not want long data to be limited by the
>> buffer).
> Not sure. Based on info from Cross, the FPGA will be available in EIM
> memory. Then it is up to the FPGA-designer to build HW to either allow
> the FPGA to read/write from other addresses (memory outside of the
> FPGA) or to expose some memory in the FPGA to SW on the CPU.

whose memory is shared would seem to make some algorithmic difference.
the green cpu would not be able to build a tlv to point to a variable
buffer in green ram.

and sharing the fpga's memory would seem to make the security issues
more severe.

need to think more.

> For my perspective, having memory in the FPGA exposed makes it easier
> for SW to do things. How that memory is then used or even implemented
> in the FPGA is another matter. It can be a simple FIFO. For example.

i suspect your fifo is my ring buffer. :)  i do not want to actually
move things.

randy