[Cryptech Core] Increasing AES core performance?

[Joachim Strömbergson]

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Aloha!

I've been looking at the performance of the AES core. Right now there
are eight Sboxes in total - four for encipher and four for decipher. The
four encipher Sboxes are also used by the key expansion. The number of
S-boxes directly affects the number of cycles it takes to perform an
AES-round.

Doing some simple test implementations shows that the resources needed
for the Sboxes scales linearly with the number of Sboxes (as expected).
Simply put, one could increase the AES performance with a factor of four
with a 26% increase in slice LUTs. It should be something like 3800 in
total. (the total have uncertainties due to removal of MUXes etc and I
haven't measured them.)

One could also decide to go for 2x performance increase with 18%
increase. Other possibilities is to only increase encipher performance.
Or be funky and increase encipher and decipher operations with different
amounts.

The question is then if this is interesting to do? Is AES performance
relevant in the current Cryptech design and for the use cases it
supports? And are there headroom in the FPGA to fit the increase in core
size?

What cipher modes are used and supported by Cryptech today? Would we
need to increase both encipher and decipher operations?


- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson
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