[Cryptech Core] Alpha rev.03

[Peter Stuge]

Fredrik Thulin wrote:
> > Thanks for sending the gerbers. While looking at JP5 AVR_GPIO it
> > seems to me like pin 10 connects to both GP3 (3v3) *and* GP4 (GND)
> > which would be a problem. Could someone else please take a look?
> 
> You mean if looking at e.g. layers GTO, G1 and G2, then G1 and G2
> both cover pin 10?

I mean GP3 and GP4, but maybe they are just two parts of a composite
layer?

If that's the case then there's another strange thing with JP3 AVR_ISP:
bottom right pin is GP4, upper right GP3. They're supposed to be GND
and 3V3 respectively.

The three last pins on SV1 (supposed to be all GND) also seem a bit
strange, all three are connected on GP4 and the two last also to GP3.


//Peter