[Cryptech Core] MKM access from FPGA

[Fredrik Thulin]

On onsdag 25 maj 2016 kl. 11:27:21 CEST Pavel Shatov wrote:
...
> Note, that AVR controls whether FPGA can access the MKM or not using
> pins MKM_CONTROL_AVR_ENA and MKM_CONTROL_FPGA_DIS. To give access to
> FPGA, we need MKM_CONTROL_AVR_ENA = 1 and MKM_CONTROL_FPGA_DIS = 0. When
> AVR is unprogrammed, those pins are high impedance and resistors R80-R81
> should by default give access to FPGA. Maybe you have the board Linus
> played with where the AVR is programmed to steal access from FPGA upon boot?

I think this guess was a good one, this is what I get when I *finally* managed 
to get the Xilinx ISE and build me a bitstream (Paul, thanks for the write-up 
on how to do that - it feels good to run my very own homemade bitstream ;) ):

Trying to adjust the clockspeed.
write  020a [ 00 00 00 20 ]
read   020a [ 00 00 00 20 ]
Trying to init to the memory in continuous mode.
write  0208 [ 00 00 00 04 ]
read   0209 [ 00 00 00 02 ]
read   0209 [ 00 00 00 03 ]
Trying to write 0xdeadbeef to the memory and then read back.
write  0210 [ 00 00 00 00 ]
write  0220 [ de ad be ef ]
write  0208 [ 00 00 00 02 ]
read   0209 [ 00 00 00 02 ]
read   0209 [ 00 00 00 03 ]
write  0210 [ 00 00 00 00 ]
write  0208 [ 00 00 00 01 ]
read   0209 [ 00 00 00 00 ]
read   0209 [ 00 00 00 03 ]
read   0220 [ de ad be ef ]
<snip some more write/reads that look happy too>

So it seems to be working for me. Paul got the unit #4, which we did all the 
initial tests on. The AVR is probably programmed with who-knows-what ;)

Paul, the hardware defaults to giving the FPGA access to the MKM. Your AVR 
must be actively preventing it, so if you can keep your AVR from booting then 
you should have access to the MKM from the FPGA.

To keep the AVR from booting, I think you can just connect the RESET pin on 
the AVR_ISP header to GND. There are a number of headers with GND marked on 
the silk screen, such as the USB UART ones, and there are three GND next to 
each other on the FPGA JTAG header. I've tested grounding my reset pin, and it 
didn't let the magic smoke out ;).

Side notes:
* I made the ISE tool produce a compressed image. Committed the change to 
core/platform/alpha/build/xilinx.mk. Size went down from 9.3 MB to 1.8, and 
the filetransfer --fpga command took me 2m21s.

* I actually ran the test without the power jumper JP4 installed (by mistake). 
It worked. I measure 2.6V at the middle pin of JP4 without the jumper 
installed - something is leaking current backwards into the 3V3_BATT. I re-ran 
the test with the jumper installed and it worked too.

Happy conclusion: The FPGA interface to the MKM works.

/Fredrik