[Cryptech Core] MKM access from FPGA

Pavel Shatov meisterpaul1 at yandex.ru
Wed May 25 08:27:21 UTC 2016


On 25.05.2016 7:57, Paul Selkirk wrote:
>
> (Tangent #1: For fun, run this under 'time' - it takes 11m40.614s at
> 921600 baud. The bitstream file is apparently a full image of the FPGA,
> so it's 9.73MB, give or take a few bytes for the length of the file
> name. This particular build compresses down to 47KB (99.5% compression
> rate), which would save 105 seconds of transmission time. But we still
> have to deal with the nearly 10 minutes that it takes to write to flash.
> This should really be its own topic.)

Actually, Xilinx tools can produce compressed bitstreams. I remember, 
that I enabled bitstream compression manually when Fredrik and I were 
doing test builds using GUI version of ISE. I think, it isn't enabled 
right now in the Makefile. Try adding "-g Compress" option to the bitgen 
command (BitGen should be the very last step of the make procedure).

> I *think* I originally mixed up miso and mosi in the .ucf file, so I
> corrected that, but with no change in output.

I think, MOSI should be W1, MISO should be Y1.

> The schematic has a  comment "CS pull-up to disable MKM by default
> (allows programming of AVR)." To effect this pull-up, I installed the
> "battery" jumper in JP4, and went from reading all 1's to all 0's.
> Change is not necessarily progress.

MKM is supposed to be battery-backed, so it will not work without that 
jumper (JP4, pins 1-2, pin 1 has square pad on the back side of the board).

> I'm sure I'm missing something simple and obvious (along the lines of
> miso/mosi or a jumper), but I can't see what it is.

Note, that AVR controls whether FPGA can access the MKM or not using 
pins MKM_CONTROL_AVR_ENA and MKM_CONTROL_FPGA_DIS. To give access to 
FPGA, we need MKM_CONTROL_AVR_ENA = 1 and MKM_CONTROL_FPGA_DIS = 0. When 
AVR is unprogrammed, those pins are high impedance and resistors R80-R81 
should by default give access to FPGA. Maybe you have the board Linus 
played with where the AVR is programmed to steal access from FPGA upon boot?


-- 
With best regards,
Pavel Shatov



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