[Cryptech Core] Berlin Slides for FPGA

[Pavel Shatov]

Hello!

I've attached the slides I'm going to show in Berlin when talking about 
the FPGA. It takes ~15 minutes to go through all of them. Is this OK?

One question I have is whether I should mention potential ASIC 
implementation or not.

If you have any other comments/suggestions, please share them. Thank you!


-- 
With best regards,
Pavel Shatov
-------------- next part --------------
A non-text attachment was scrubbed...
Name: CrypTech_FPGA.odp
Type: application/vnd.oasis.opendocument.presentation
Size: 204443 bytes
Desc: not available
URL: <https://lists.cryptech.is/archives/core/attachments/20160713/a71adfcc/attachment-0001.odp>