[Cryptech Core] nit: reset low or high

Joachim Strömbergson joachim at secworks.se
Thu Mar 12 11:44:16 UTC 2015


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Aloha!

Paul Selkirk wrote:
> I don't recall the conversation about reset levels, so I apologize
> for rehashing it. I do vaguely recall a conversation about synch vs
> asynch reset, but I didn't have an informed opinion then (nor do I
> now).

We discussed it on a meeting and I also posted reset strategy
differences between Altera and Xilinx on the maillist.

My experience is also that active low reset is generally much more
common. Also, we have substantially more cores with active low reset
than active high.

Since they are clocked and a slow signal we can always add an inverter
to get the same behaviour for top level active high reset modules. But
changing code in all cores to active high reset would take more work
than changing the top level stuff for the Novena. And imho make the
cores (slightly) less usable for example in an ARM system using the
standard AMBA buses.


> So we have one vote for active-high, and one for active-low. I'm not
> an FPGA guy, so I don't have a strong opinion, but I know
> inconsistency when I see it, so I do have a strong opinion that it
> should be one or the other.

Stuge seems to think active low is the common choice too.

- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
========================================================================
 Joachim Strömbergson          Secworks AB          joachim at secworks.se
========================================================================
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