[Cryptech Core] proposed core reorganization

[Павел Шатов]

On 05.03.2015 16:39, Joachim Strömbergson wrote:
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> Aloha!
>
> Павел Шатов wrote:
>> 1. Use conditional synthesis and instantiate appropriate modules
>> inside of hash_selector.v in `ifdef NO	VENA and `ifdef TERASIC
>> blocks. I don't know why you dislike conditional synthesis, it is a
>> common trick. Yes, it looks ugly at times, but universality involves
>> increased complexity, you can't do anything about it.
>
> Yes, I dislike conditional synthesis. I usually do it by separate scripts.

You mean, you have some separate preprocessor-like script, that you run 
before you synthesize your project to modify Verilog files in some way 
or what?

>
>> 2. Make hash_selector_novena.v that instantiates novena_regs.v and
>> hash_selector_terasic.v that instantiates terasic_regs.v. This way
>> hash selector becomes in fact platform-specific and your decision to
>> place core_selector under platform makes even more sense.
>
> If possible, those registers should really be in the EIM and/or
> queue/clock domain crossing modules, not in core_selector. The
> core_selector is (should be) basically an address decoded and mux and
> not have tech specific instances.

My original idea is to have a register with some fixed address, say 
0x0000, that will read as 0xAAAAAAAA when our project is run on Novena, 
0xBBBBBBBB when our project is run on Terasic C5G, 0xCCCCCCCC when our 
project is run on Alpha Board and so on. This register should be placed 
in a separate module. The question is where to instantiate this module.

If you want to place this module inside of EIM arbiter in Novena, you 
need to place it in UART interface for Terasic too. In this case you 
will end up not having separate EIM & UART interfaces, but some mutant 
EIM + global register and UART + global register interfaces. Moreover 
such partitioning will require additional multiplexor in EIM and UART 
interfaces. We already have multiplexors in core_selector, joining 
several multiplexors in series is not a very good practice.

I suggest that we instantiate global register module instead of one of 
the cores. You can create a separate Verilog file, say 
global_registers.v with the following content. It will hide all the 
"ugly" code from core_selector.v

`define BUILD_NOVENA
/* `define BUILD_TERASIC */
/* `define BUILD_ALPHA */

`ifdef BUILD_NOVENA
global_regs_novena global_regs
(
...
);
`endif

`ifdef BUILD_TERASIC
global_regs_terasic global_regs
(
...
);
`endif

`ifdef BUILD_ALPHA
global_regs_alpha global_regs
(
...
);
`endif

Preprocessor is a very powerful feature of C/C++, why don't you guys 
want to use its equivalent in Verilog?

--
With best regards,
Pavel Shatov