[Cryptech Core] Schematic and Board Layout timetable

[Jacob]

Saw the discussion about the time table and thought to add some comments:

Schematic:
The alpha block diagram simplicity is misleading. There are required 
functional parts that are missing from it.
Time estimate takes into consideration the actual design of the 
sub-circuits and components selection (not a trivial task).
Also, a consensus for each sub-section design is required by the 
core/tech group - taxing progress.

For example, some missing sections:

- Power supplies design (including 3A PS for the FPGA, Vtt power supply 
for the DDR3, Power sequencing for the FPGA etc.)
- Documents mentioned LCD. Is it on board or external? Regardless, need 
to design it in.
- HSM might be installed in a server room. How do you notify Sysadmin in 
case of tampering? UART signalling to an isolated Ethernet sub-system? 
no notification? And will you notify the sysadmin if suddenly the RNG 
acts "funny" or the anti-tamper battery is drained out?
- There are three batteries in the design: MKM, Anti-Tamper, RTC.
Are all 3 replaceable (meaning 3 battery holders and a a required simple 
method to reach them)? Do we have room on the board for all 3 or do we 
distribute power from one master battery?

And so on.

PCB Layout:

The 3-4 months estimate was for 75% availability, including speculative 
2 Design changes mid-course. To have everything fits in on an 75X130mm 
board is not trivial, especially if LCD is added, or, god forbids, the 
DDR3 chips will be on board (point-to-point i.e. no socket).

Controlled impedance for the DDR3 and USB lines, 3A+ very low impedance 
planes for the FPGA, possible potting of a sub-circuit are part of the 
layout effort. Also included in the estimate is SI/PI and thermal analysis.

Jacob