[Cryptech Core] meeting 28th and 29th

[Joachim Strömbergson]

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Aloha!

Leif Johansson wrote:
>> My plan is to adapt xobs's novena-ws2312b-fpga project to talk
>> directly to the SHA-1 core (and later the SHA-256 and SHA-512
>> cores) over the I2C interface. Briefly, I2C is a 2-wire serial bus
>> with its own device addressing scheme, so this would replace the
>> uart and coretest bits of the coretest_hashes project.
> 
> Is that how the fpga is connected then? Interesting...

No. The main application interface between the ARM CPU and the FPGA is
the EBM interface. It is a wide, low latency memory like interface
suitable for adding application specific coprocessors to the CPU. It is
the interface Bunnie and xobs intend to use to do useful stuff with the
FPGA on Novena. We should support the development of the necessary SW
and HW design to allow easy implementation of custom application HW for
Novena.

Building a Cryptech HSM with the upper layers in SW on the CPU and HW in
the FPGA connected via I2C will not be useful for many of the use cases.
The latency just to get data back and forth between the CPU and FPGA
will make any performance requirements basically impossible to meet.

But starting with I2C is not wrong at all. It will allow us to start
testing Cryptech HW and SW interaction on Novena. But I really think
that we should focus on the EBM interface quite soon.

- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
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 Joachim Strömbergson          Secworks AB          joachim at secworks.se
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