[Cryptech Core] Fwd: FPGA issues (Was: Re: Current sync problem)

Joachim Strömbergson joachim at secworks.se
Mon Dec 22 08:46:15 UTC 2014


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Aloha!

Randy Bush wrote:
> on the last call basil said something akin to a synchronous buffer,
> no clock, just signal buffer empty, wait for other side to say buffer
> is now full.  stupid enough even i could fool myself that i
> understood what he was saying.

Not sure I understand. You would need at least one clock in any
construct that handles clock domain boundary crossing. a fully
asynchronous block will not be able to hold any info and will also be
hard to get stable. Its behaviour will vary with placement on the FPGA
structure.

But it also sounds a bit like what I ment with a fifo where you have
syn- and ack-signals on both ends. The depth of the fifo can be as
little as one, but not less than that. In our case the fifo fed from the
clk133 domain would have at least storage for two elements to allow the
handling of double data rate.

You want to have ack-signals to allow inserting and extracting entities
connected to the fifo to know that their requests has been acknowledged.

If that is close to what Basil and you are thinking about then yes it
should potentially solve the boundary crossing issues. But the timing on
the EIM bus needs to be solved. And cleaning up the clock implementation
will quite probably also be needed.

- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
========================================================================
 Joachim Strömbergson          Secworks AB          joachim at secworks.se
========================================================================
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