[Cryptech Core] Fwd: FPGA issues (Was: Re: Current sync problem)

Randy Bush randy at psg.com
Fri Dec 19 16:55:08 UTC 2014


on the last call basil said something akin to a synchronous buffer, no
clock, just signal buffer empty, wait for other side to say buffer is
now full.  stupid enough even i could fool myself that i understood what
he was saying.

randy



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