[Cryptech-Commits] [core/util/keywrap] 68/95: Killed the bank switching.

[git at cryptech.is]

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paul at psgd.org pushed a commit to branch master
in repository core/util/keywrap.

commit e27c1afd9801512ad9cb2b2e23b5eeed1a28a381
Author: Joachim Strömbergson <joachim at secworks.se>
AuthorDate: Fri Aug 24 10:59:07 2018 +0200

    Killed the bank switching.
---
 src/rtl/keywrap.v | 23 ++++-------------------
 1 file changed, 4 insertions(+), 19 deletions(-)

diff --git a/src/rtl/keywrap.v b/src/rtl/keywrap.v
index f55545f..e0bda45 100644
--- a/src/rtl/keywrap.v
+++ b/src/rtl/keywrap.v
@@ -82,7 +82,6 @@ module keywrap #(parameter ADDR_BITS = 15)
   localparam CTRL_KEYLEN_BIT  = 1;
 
   localparam ADDR_RLEN        = 8'h0c;
-  localparam ADDR_R_BANK      = 8'h0d;
   localparam ADDR_A0          = 8'h0e;
   localparam ADDR_A1          = 8'h0f;
 
@@ -123,9 +122,6 @@ module keywrap #(parameter ADDR_BITS = 15)
   reg [12 : 0] rlen_reg;
   reg          rlen_we;
 
-  reg [6 : 0]  r_bank_reg;
-  reg          r_bank_we;
-
   reg [31 : 0] a0_reg;
   reg          a0_we;
 
@@ -149,7 +145,7 @@ module keywrap #(parameter ADDR_BITS = 15)
   reg            tmp_error;
 
   reg            core_api_we;
-  wire [13 : 0]  core_api_addr;
+  wire [(MEM_BITS - 1) : 0] core_api_addr;
   wire           core_ready;
   wire           core_valid;
   wire [255 : 0] core_key;
@@ -167,7 +163,7 @@ module keywrap #(parameter ADDR_BITS = 15)
   assign core_key = {key_reg[0], key_reg[1], key_reg[2], key_reg[3],
                      key_reg[4], key_reg[5], key_reg[6], key_reg[7]};
 
-  assign core_api_addr = {r_bank_reg, address[6 : 0]};
+  assign core_api_addr = address[(MEM_BITS - 1) : 0];
 
   assign core_a_init = {a0_reg, a1_reg};
 
@@ -218,8 +214,7 @@ module keywrap #(parameter ADDR_BITS = 15)
           next_reg         <= 1'h0;
           encdec_reg       <= 1'h0;
           keylen_reg       <= 1'h0;
-          r_bank_reg       <= 7'h0;
-          rlen_reg         <= 13'h0;
+         rlen_reg         <= 13'h0;
           valid_reg        <= 1'h0;
           ready_reg        <= 1'h0;
           a0_reg           <= 32'h0;
@@ -240,9 +235,6 @@ module keywrap #(parameter ADDR_BITS = 15)
               keylen_reg <= write_data[CTRL_KEYLEN_BIT];
             end
 
-          if (r_bank_we)
-            r_bank_reg <= write_data[6 : 0];
-
           if (rlen_we)
             rlen_reg <= write_data[12 : 0];
 
@@ -269,7 +261,6 @@ module keywrap #(parameter ADDR_BITS = 15)
       next_new         = 1'h0;
       config_we        = 1'h0;
       rlen_we          = 1'h0;
-      r_bank_we        = 1'h0;
       key_we           = 1'h0;
       core_api_we      = 1'h0;
       a0_we            = 1'h0;
@@ -300,9 +291,6 @@ module keywrap #(parameter ADDR_BITS = 15)
               if (address == {{PAD{1'h0}}, ADDR_RLEN})
                 rlen_we = 1'h1;
 
-              if (address == {{PAD{1'h0}}, ADDR_R_BANK})
-                r_bank_we = 1'h1;
-
               if (address == {{PAD{1'h0}}, ADDR_A0})
                 a0_we = 1'h1;
 
@@ -313,7 +301,7 @@ module keywrap #(parameter ADDR_BITS = 15)
                    (address <= {{PAD{1'h0}}, ADDR_KEY7}))
                 key_we = 1'h1;
 
-              if (address >= ADDR_R_DATA0 && address <= ADDR_R_DATA127)
+              if (address[(ADDR_BITS - 1)])
                 core_api_we = 1'h1;
             end // if (we)
           else
@@ -337,9 +325,6 @@ module keywrap #(parameter ADDR_BITS = 15)
               if (address == {{PAD{1'h0}}, ADDR_RLEN})
                 api_rd_delay_new = {19'h0, rlen_reg};
 
-              if (address == {{PAD{1'h0}}, ADDR_R_BANK})
-                api_rd_delay_new = {25'h0, r_bank_reg};
-
               if (address == {{PAD{1'h0}}, ADDR_A0})
                 api_rd_delay_new = core_a_result[63 : 32];