[Cryptech-Commits] [core/util/keywrap] 67/95: Performed Verilog parameter magic to make the design scaleable in terms of capacity. Does not yet work, but at least the linter is fairly happy.
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Wed Mar 25 17:19:06 UTC 2020
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paul at psgd.org pushed a commit to branch master
in repository core/util/keywrap.
commit 860dc811015211ac41a33275d974434c323f7422
Author: Joachim Strömbergson <joachim at secworks.se>
AuthorDate: Fri Aug 24 10:44:10 2018 +0200
Performed Verilog parameter magic to make the design scaleable in terms of capacity. Does not yet work, but at least the linter is fairly happy.
---
src/rtl/keywrap.v | 94 ++++++++++++++++++++++++--------------------------
src/rtl/keywrap_core.v | 66 ++++++++++++++++++-----------------
src/rtl/keywrap_mem.v | 58 +++++++++++++++++--------------
3 files changed, 112 insertions(+), 106 deletions(-)
diff --git a/src/rtl/keywrap.v b/src/rtl/keywrap.v
index 6a28133..f55545f 100644
--- a/src/rtl/keywrap.v
+++ b/src/rtl/keywrap.v
@@ -4,6 +4,17 @@
// --------
// Top level wrapper for the KEY WRAP core.
//
+// Since $clog2() is not supported by all tools, and constant
+// functions are not supported by some other tools we need to
+// do the size to number of bits calculation by hand.
+// 8192 bytes = 2048 32 bit words. This requires 11 bits.
+// We need additional space for control and status words. But
+// since we have filled the address space, we need another MSB
+// in the address. Thus ADDR_BITS = 12 bits.
+//
+// 0x000 - 0x7ff are for control and status.
+// 0x800 - 0xfff are for data storage
+//
//
// Author: Joachim Strombergson
// Copyright (c) 2018, NORDUnet A/S
@@ -37,38 +48,19 @@
//
//======================================================================
-module keywrap(
- // Clock and reset.
- input wire clk,
- input wire reset_n,
+module keywrap #(parameter ADDR_BITS = 15)
+ (
+ input wire clk,
+ input wire reset_n,
- // Control.
- input wire cs,
- input wire we,
-
- // Data ports.
- input wire [(ASPACE - 1) : 0] address,
- input wire [31 : 0] write_data,
- output wire [31 : 0] read_data,
- output wire error
- );
-
- //----------------------------------------------------------------
- // External parameters
- //----------------------------------------------------------------
- // Since $clog2() is not supported by all tools, and constant
- // functions are not supported by some other tools we need to
- // do the size to number of bits calculation by hand.
- // 8192 bytes = 2048 32 bit words. This requires 11 bits.
- // We need additional space for control and status words. But
- // since we have filled the address space, we need another MSB
- // in the address - 12 bits.
- //
- // 0x000 - 0x7ff are for control and status.
- // 0x800 - 0xfff are for data storage
- parameter ASPACE = 12;
- localparam MEM_SPACE = (ASPACE / 2);
+ input wire cs,
+ input wire we,
+ input wire [(ADDR_BITS - 1) : 0] address,
+ input wire [31 : 0] write_data,
+ output wire [31 : 0] read_data,
+ output wire error
+ );
//----------------------------------------------------------------
// Internal constant and parameter definitions.
@@ -108,7 +100,11 @@ module keywrap(
localparam CORE_NAME0 = 32'h6b657920; // "key "
localparam CORE_NAME1 = 32'h77726170; // "wrap"
- localparam CORE_VERSION = 32'h302e3731; // "0.71"
+ localparam CORE_VERSION = 32'h302e3830; // "0.80"
+
+
+ localparam MEM_BITS = ADDR_BITS - 1;
+ localparam PAD = ADDR_BITS - 8;
//----------------------------------------------------------------
@@ -179,7 +175,8 @@ module keywrap(
//----------------------------------------------------------------
// core instantiation.
//----------------------------------------------------------------
- keywrap_core core(
+ keywrap_core #(.MEM_BITS(MEM_BITS))
+ core(
.clk(clk),
.reset_n(reset_n),
@@ -291,28 +288,29 @@ module keywrap(
begin
if (we)
begin
- if (address == ADDR_CTRL)
+ if (address == {{PAD{1'h0}}, ADDR_CTRL})
begin
init_new = write_data[CTRL_INIT_BIT];
next_new = write_data[CTRL_NEXT_BIT];
end
- if (address == ADDR_CONFIG)
+ if (address == {{PAD{1'h0}}, ADDR_CONFIG})
config_we = 1'h1;
- if (address == ADDR_RLEN)
+ if (address == {{PAD{1'h0}}, ADDR_RLEN})
rlen_we = 1'h1;
- if (address == ADDR_R_BANK)
+ if (address == {{PAD{1'h0}}, ADDR_R_BANK})
r_bank_we = 1'h1;
- if (address == ADDR_A0)
+ if (address == {{PAD{1'h0}}, ADDR_A0})
a0_we = 1'h1;
- if (address == ADDR_A1)
+ if (address == {{PAD{1'h0}}, ADDR_A1})
a1_we = 1'h1;
- if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7))
+ if ((address >= {{PAD{1'h0}}, ADDR_KEY0}) &&
+ (address <= {{PAD{1'h0}}, ADDR_KEY7}))
key_we = 1'h1;
if (address >= ADDR_R_DATA0 && address <= ADDR_R_DATA127)
@@ -321,31 +319,31 @@ module keywrap(
else
begin
// Read access
- if (address == ADDR_NAME0)
+ if (address == {{PAD{1'h0}}, ADDR_NAME0})
api_rd_delay_new = CORE_NAME0;
- if (address == ADDR_NAME1)
+ if (address == {{PAD{1'h0}}, ADDR_NAME1})
api_rd_delay_new = CORE_NAME1;
- if (address == ADDR_VERSION)
+ if (address == {{PAD{1'h0}}, ADDR_VERSION})
api_rd_delay_new = CORE_VERSION;
- if (address == ADDR_CTRL)
+ if (address == {{PAD{1'h0}}, ADDR_CTRL})
api_rd_delay_new = {28'h0, keylen_reg, encdec_reg, next_reg, init_reg};
- if (address == ADDR_STATUS)
+ if (address == {{PAD{1'h0}}, ADDR_STATUS})
api_rd_delay_new = {30'h0, valid_reg, ready_reg};
- if (address == ADDR_RLEN)
+ if (address == {{PAD{1'h0}}, ADDR_RLEN})
api_rd_delay_new = {19'h0, rlen_reg};
- if (address == ADDR_R_BANK)
+ if (address == {{PAD{1'h0}}, ADDR_R_BANK})
api_rd_delay_new = {25'h0, r_bank_reg};
- if (address == ADDR_A0)
+ if (address == {{PAD{1'h0}}, ADDR_A0})
api_rd_delay_new = core_a_result[63 : 32];
- if (address == ADDR_A1)
+ if (address == {{PAD{1'h0}}, ADDR_A1})
api_rd_delay_new = core_a_result[31 : 0];
end // else: !if(we)
end // if (cs)
diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v
index 8d8f101..d1e63b0 100644
--- a/src/rtl/keywrap_core.v
+++ b/src/rtl/keywrap_core.v
@@ -40,29 +40,30 @@
//
//======================================================================
-module keywrap_core (
- input wire clk,
- input wire reset_n,
+module keywrap_core #(parameter MEM_BITS = 11)
+ (
+ input wire clk,
+ input wire reset_n,
- input wire init,
- input wire next,
- input wire encdec,
+ input wire init,
+ input wire next,
+ input wire encdec,
- output wire ready,
- output wire valid,
+ output wire ready,
+ output wire valid,
- input wire [12 : 0] rlen,
+ input wire [(MEM_BITS - 2) : 0] rlen,
- input wire [255 : 0] key,
- input wire keylen,
+ input wire [255 : 0] key,
+ input wire keylen,
- input wire [63 : 0] a_init,
- output wire [63 : 0] a_result,
+ input wire [63 : 0] a_init,
+ output wire [63 : 0] a_result,
- input wire api_we,
- input wire [13 : 0] api_addr,
- input wire [31 : 0] api_wr_data,
- output wire [31 : 0] api_rd_data
+ input wire api_we,
+ input wire [(MEM_BITS - 1) : 0] api_addr,
+ input wire [31 : 0] api_wr_data,
+ output wire [31 : 0] api_rd_data
);
@@ -100,13 +101,13 @@ module keywrap_core (
reg valid_new;
reg valid_we;
- reg [12 : 0] block_ctr_reg;
- reg [12 : 0] block_ctr_new;
- reg block_ctr_we;
- reg block_ctr_dec;
- reg block_ctr_inc;
- reg block_ctr_rst;
- reg block_ctr_set;
+ reg [(MEM_BITS - 2) : 0] block_ctr_reg;
+ reg [(MEM_BITS - 2) : 0] block_ctr_new;
+ reg block_ctr_we;
+ reg block_ctr_dec;
+ reg block_ctr_inc;
+ reg block_ctr_rst;
+ reg block_ctr_set;
reg [2 : 0] iteration_ctr_reg;
reg [2 : 0] iteration_ctr_new;
@@ -133,16 +134,17 @@ module keywrap_core (
reg update_state;
- reg core_we;
- reg [12 : 0] core_addr;
- reg [63 : 0] core_wr_data;
- wire [63 : 0] core_rd_data;
+ reg core_we;
+ reg [(MEM_BITS - 2) : 0] core_addr;
+ reg [63 : 0] core_wr_data;
+ wire [63 : 0] core_rd_data;
//----------------------------------------------------------------
// Instantiations.
//----------------------------------------------------------------
- keywrap_mem mem(
+ keywrap_mem #(.API_ADDR_BITS(MEM_BITS))
+ mem(
.clk(clk),
.api_we(api_we),
@@ -194,7 +196,7 @@ module keywrap_core (
a_reg <= 64'h0;
ready_reg <= 1'h1;
valid_reg <= 1'h1;
- block_ctr_reg <= 13'h0;
+ block_ctr_reg <= {(MEM_BITS - 1){1'h0}};
iteration_ctr_reg <= 3'h0;
keywrap_core_ctrl_reg <= CTRL_IDLE;
end
@@ -269,12 +271,12 @@ module keywrap_core (
//----------------------------------------------------------------
always @*
begin : block_ctr
- block_ctr_new = 13'h0;
+ block_ctr_new = {(MEM_BITS - 1){1'h0}};
block_ctr_we = 1'h0;
if (block_ctr_rst)
begin
- block_ctr_new = 13'h0;
+ block_ctr_new = {(MEM_BITS - 1){1'h0}};
block_ctr_we = 1'h1;
end
diff --git a/src/rtl/keywrap_mem.v b/src/rtl/keywrap_mem.v
index 6a70ebe..9d8e63d 100644
--- a/src/rtl/keywrap_mem.v
+++ b/src/rtl/keywrap_mem.v
@@ -37,33 +37,39 @@
//
//======================================================================
-module keywrap_mem (
- input wire clk,
-
- input wire api_we,
- input wire [13 : 0] api_addr,
- input wire [31 : 0] api_wr_data,
- output wire [31 : 0] api_rd_data,
-
- input wire core_we,
- input wire [12 : 0] core_addr,
- input wire [63 : 0] core_wr_data,
- output wire [63 : 0] core_rd_data
+module keywrap_mem #(parameter API_ADDR_BITS = 11)
+ (
+ input wire clk,
+
+ input wire api_we,
+ input wire [(API_ADDR_BITS - 1) : 0] api_addr,
+ input wire [31 : 0] api_wr_data,
+ output wire [31 : 0] api_rd_data,
+
+ input wire core_we,
+ input wire [(API_ADDR_BITS - 2) : 0] core_addr,
+ input wire [63 : 0] core_wr_data,
+ output wire [63 : 0] core_rd_data
);
+ //----------------------------------------------------------------
+ // Parameters.
+ //----------------------------------------------------------------
+ localparam NUM_BANK_WORDS = 2 ** (API_ADDR_BITS - 1);
+
//----------------------------------------------------------------
// Registers and memories including control signals.
//----------------------------------------------------------------
- reg [31 : 0] mem0 [0 : 8191];
- reg [31 : 0] mem0_data;
- reg [12 : 0] mem0_addr;
- reg mem0_we;
+ reg [31 : 0] mem0 [0 : (NUM_BANK_WORDS - 1)];
+ reg [31 : 0] mem0_data;
+ reg [(API_ADDR_BITS - 2) : 0] mem0_addr;
+ reg mem0_we;
- reg [31 : 0] mem1 [0 : 8191];
- reg [31 : 0] mem1_data;
- reg [12 : 0] mem1_addr;
- reg mem1_we;
+ reg [31 : 0] mem1 [0 : (NUM_BANK_WORDS - 1)];
+ reg [31 : 0] mem1_data;
+ reg [(API_ADDR_BITS - 2) : 0] mem1_addr;
+ reg mem1_we;
//----------------------------------------------------------------
@@ -90,7 +96,7 @@ module keywrap_mem (
always @(posedge clk)
begin : mem0_access
core_rd_data0 <= mem0[core_addr];
- api_rd_data0 <= mem0[api_addr[13 : 1]];
+ api_rd_data0 <= mem0[api_addr[(API_ADDR_BITS - 1) : 1]];
if (mem0_we)
mem0[mem0_addr] <= mem0_data;
@@ -103,7 +109,7 @@ module keywrap_mem (
always @(posedge clk)
begin : mem1_access
core_rd_data1 <= mem1[core_addr];
- api_rd_data1 <= mem1[api_addr[13 : 1]];
+ api_rd_data1 <= mem1[api_addr[(API_ADDR_BITS - 1) : 1]];
if (mem1_we)
mem1[mem1_addr] <= mem1_data;
@@ -130,10 +136,10 @@ module keywrap_mem (
always @*
begin : write_mux
mem0_data = 32'h0;
- mem0_addr = 13'h0;
+ mem0_addr = {(API_ADDR_BITS - 1){1'h0}};
mem0_we = 1'h0;
mem1_data = 32'h0;
- mem1_addr = 13'h0;
+ mem1_addr = {(API_ADDR_BITS - 1){1'h0}};
mem1_we = 1'h0;
if (core_we)
@@ -148,9 +154,9 @@ module keywrap_mem (
else if (api_we)
begin
- mem0_addr = api_addr[13 : 1];
+ mem0_addr = api_addr[(API_ADDR_BITS - 1) : 1];
mem0_data = api_wr_data;
- mem1_addr = api_addr[13 : 1];
+ mem1_addr = api_addr[(API_ADDR_BITS - 1) : 1];
mem1_data = api_wr_data;
if (api_addr[0])
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