January 2020 Archives by author
Starting: Wed Jan 1 19:27:50 UTC 2020
Ending: Sun Jan 26 09:37:28 UTC 2020
Messages: 47
- [Cryptech-Commits] [releng/alpha] branch master updated: Accumulated minor changes on master branches
git at cryptech.is
- [Cryptech-Commits] [releng/alpha] branch fmc_clk updated: Accumulated minor changes on fmc_clk branches
git at cryptech.is
- [Cryptech-Commits] [user/shatov/modexpng_fpga_model] branch master updated: * mostly cosmetic fixes related to debug output * fixed REGULAR_ADD opcode to match how hardware works
git at cryptech.is
- [Cryptech-Commits] [user/shatov/modexpng] branch master updated (6791175 -> 97d5b79)
git at cryptech.is
- [Cryptech-Commits] [user/shatov/modexpng] 01/21: Had to rework the general worker module to reach 180 MHz core clock. The module is responsible for doing certain supporting operations (mostly moving operands between banks and doing some simple math operations, such as modular subtraction and regular addition). Depending on the particular operation, one of three bank address space sweep patterns was used: * one-pass (for things like carry propagation) * two-pass (for things like modular subtraction that produce intermediate values in [...]
git at cryptech.is
- [Cryptech-Commits] [user/shatov/modexpng] 02/21: Turns out, fabric addition and subtraction in the general worker module are actually in the critical paths of the ModExpNG core and are plaguing the place and route tools. I was barely able to achieve timing closure at 180 MHz even with the highest Map and PaR effort levels. This means that any further clock frequency increase is effectively impossible, moreover any small change in the design may prevent it from meeting timing constants. The obvious solution is to use DSP slices not only f [...]
git at cryptech.is
- [Cryptech-Commits] [user/shatov/modexpng] 03/21: Reworked modular subtraction micro-operation. Previously it used "two-pass" bank address space sweep, during the first pass (a-b) and (a-b+n) were computed, during the second pass either the former or the latter quantity was written to the output bank (depending on the very last borrow flag value). This is no longer possible, since the FSM now only generates one "interleaved" address space sweep. The solution is to split one complex modular subtraction operation into simpler sub-operations [...]
git at cryptech.is
- [Cryptech-Commits] [user/shatov/modexpng] 04/21: This commit modifies the REGULAR_ADD_UNEVEN micro-operation to use DSP slices for addition instead of fabric logic. This opcode is only necessary when in CRT mode and is executed once per entire exponentiation to recombine the two "easier" exponentiations. This was the final change necessary to get rid of using fabric math in the general worker module.
git at cryptech.is
- [Cryptech-Commits] [user/shatov/modexpng] 05/21: * DSP slices now have two use modes: MULT and ADD/SUB * cosmetic rename of Verilog include file
git at cryptech.is
- [Cryptech-Commits] [user/shatov/modexpng] 06/21: Removed old DSP wrappers.
git at cryptech.is
- [Cryptech-Commits] [user/shatov/modexpng] 07/21: Added two pairs of new wrappers.
git at cryptech.is
- [Cryptech-Commits] [user/shatov/modexpng] 08/21: Cosmetic fix that only involves debug output during simulation.
git at cryptech.is
- [Cryptech-Commits] [user/shatov/modexpng] 09/21: Updated microcode source to match the changes made to general worker module.
git at cryptech.is
- [Cryptech-Commits] [user/shatov/modexpng] 10/21: Updated uOP engine to match the changes made to the general worker module (modular subtraction was split into three micro-operations instead of one).
git at cryptech.is
- [Cryptech-Commits] [user/shatov/modexpng] 11/21: For the new general worker module to work we need dynamic switching of DSP OPMODE, ALUMODE and CARRYINSEL ports, thus more defined constants.
git at cryptech.is
- [Cryptech-Commits] [user/shatov/modexpng] 12/21: Tiny cosmetic typo fix ("dst" -> "dsp")
git at cryptech.is
- [Cryptech-Commits] [user/shatov/modexpng] 13/21: Added more meaningful constants to avoid certain hardcoded numbers.
git at cryptech.is
- [Cryptech-Commits] [user/shatov/modexpng] 14/21: Refactored modular reductor module.
git at cryptech.is
- [Cryptech-Commits] [user/shatov/modexpng] 15/21: Renumbered micro-operations.
git at cryptech.is
- [Cryptech-Commits] [user/shatov/modexpng] 16/21: The I/O manager has to work in sync with the general worker module. Made the necessary changes to make it work after the general worker update. Also moved debug simulation-time code into a separate file.
git at cryptech.is
- [Cryptech-Commits] [user/shatov/modexpng] 17/21: Update DSP wrapper instance names.
git at cryptech.is
- [Cryptech-Commits] [user/shatov/modexpng] 18/21: Refactored MMM recombinator module, accomodated the changes in DSP slice wrapper names.
git at cryptech.is
- [Cryptech-Commits] [user/shatov/modexpng] 19/21: Refactored the MMM module, now uses meaningful constant names from the include file, not hardcoded widths.
git at cryptech.is
- [Cryptech-Commits] [user/shatov/modexpng] 20/21: Cosmetic change to easily switch tests on/off.
git at cryptech.is
- [Cryptech-Commits] [user/shatov/modexpng] 21/21: Bump version number.
git at cryptech.is
- [Cryptech-Commits] [sw/stm32] branch fmc_clk updated (4ac1beb -> 723766c)
git at cryptech.is
- [Cryptech-Commits] [sw/stm32] 01/02: Updated FMC initialization code to match changes in FMC arbiter.
git at cryptech.is
- [Cryptech-Commits] [sw/stm32] 02/02: New FMC settings for STM32.
git at cryptech.is
- [Cryptech-Commits] [user/ln5/stm32-avalanche-noise] branch ln/devel updated (6f4f2af -> e775954)
git at cryptech.is
- [Cryptech-Commits] [user/ln5/stm32-avalanche-noise] 01/02: Add version and application info to ELF file
git at cryptech.is
- [Cryptech-Commits] [user/ln5/stm32-avalanche-noise] 02/02: Update comments for later revisions
git at cryptech.is
- [Cryptech-Commits] [core/platform/alpha] branch fmc_clk_core created (now c85809c)
git at cryptech.is
- [Cryptech-Commits] [core/platform/alpha] 01/07: New Alpha platform with three clocks: * 45 MHz (aka "io_clk") is the I/O clock for the FMC bus * 90 MHz (aka "sys_clk") is the system clock for all the cores * 180 MHz (aka "core_clk") is the high-speed clock for high-performance cores
git at cryptech.is
- [Cryptech-Commits] [core/platform/alpha] 02/07: Bumped version number.
git at cryptech.is
- [Cryptech-Commits] [core/platform/alpha] 03/07: Testbench for the new clock manager.
git at cryptech.is
- [Cryptech-Commits] [core/platform/alpha] 04/07: Tweak the Makefile to match the new Alpha platform.
git at cryptech.is
- [Cryptech-Commits] [core/platform/alpha] 05/07: This commit turns off the "equivalent_register_removal" setting for XST.
git at cryptech.is
- [Cryptech-Commits] [core/platform/alpha] 06/07: Changed FMC I/O frequency to 45 MHz in the UCF file to match hardware and also updated offset constraint values accordingly.
git at cryptech.is
- [Cryptech-Commits] [core/platform/alpha] 07/07: Out of curiosity I tried compiling the bitstream with Vivado. These constraints may come handy if you're brave enough to try this at home.
git at cryptech.is
- [Cryptech-Commits] [user/ln5/stm32-avalanche-noise] branch master updated (15f056c -> be1d685)
git at cryptech.is
- [Cryptech-Commits] [user/ln5/stm32-avalanche-noise] 01/05: [cc20rng] Code formatting changes
git at cryptech.is
- [Cryptech-Commits] [user/ln5/stm32-avalanche-noise] 02/05: [cc20rng] Revamping the ChaCha20 seeding
git at cryptech.is
- [Cryptech-Commits] [user/ln5/stm32-avalanche-noise] 03/05: Merge branch 'ln/cc20rng-revamp' into ln/devel
git at cryptech.is
- [Cryptech-Commits] [user/ln5/stm32-avalanche-noise] 04/05: [entropy] Raise USB baud rate to match application 'cc20rng'
git at cryptech.is
- [Cryptech-Commits] [user/ln5/stm32-avalanche-noise] 05/05: Revert "Add version and application info to ELF file"
git at cryptech.is
- [Cryptech-Commits] [user/ln5/stm32-avalanche-noise] annotated tag base-1.0.0 created (now 4e12187)
git at cryptech.is
- [Cryptech-Commits] [user/ln5/stm32-avalanche-noise] annotated tag cc20rng-1.0.0 created (now c714954)
git at cryptech.is
Last message date:
Sun Jan 26 09:37:28 UTC 2020
Archived on: Sun Jan 26 09:37:34 UTC 2020
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