[Cryptech-Commits] [user/shatov/modexpng] branch master updated (6791175 -> 97d5b79)

git at cryptech.is git at cryptech.is
Mon Jan 20 21:18:01 UTC 2020

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meisterpaul1 at yandex.ru pushed a change to branch master
in repository user/shatov/modexpng.

    from 6791175  One more cosmetic fix.
     new 83f8779  Had to rework the general worker module to reach 180 MHz core clock. The module is responsible for doing certain supporting operations (mostly moving operands between banks and doing some simple math operations, such as modular subtraction and regular addition). Depending on the particular operation, one of three bank address space sweep patterns was used:  * one-pass (for things like carry propagation)  * two-pass (for things like modular subtraction that produce interm [...]
     new 6a0438e  Turns out, fabric addition and subtraction in the general worker module are actually in the critical paths of the ModExpNG core and are plaguing the place and route tools. I was barely able to achieve timing closure at 180 MHz even with the highest Map and PaR effort levels. This means that any further clock frequency increase is effectively impossible, moreover any small change in the design may prevent it from meeting timing constants. The obvious solution is to use DS [...]
     new e5f4454  Reworked modular subtraction micro-operation. Previously it used "two-pass" bank address space sweep, during the first pass (a-b) and (a-b+n) were computed, during the second pass either the former or the latter quantity was written to the output bank (depending on the very last borrow flag value). This is no longer possible, since the FSM now only generates one "interleaved" address space sweep. The solution is to split one complex modular subtraction operation into sim [...]
     new ab061af  This commit modifies the REGULAR_ADD_UNEVEN micro-operation to use DSP slices for addition instead of fabric logic. This opcode is only necessary when in CRT mode and is executed once per entire exponentiation to recombine the two "easier" exponentiations. This was the final change necessary to get rid of using fabric math in the general worker module.
     new b985d45   * DSP slices now have two use modes: MULT and ADD/SUB  * cosmetic rename of Verilog include file
     new 147dcd3  Removed old DSP wrappers.
     new a1314f3  Added two pairs of new wrappers.
     new b585d25  Cosmetic fix that only involves debug output during simulation.
     new b590661  Updated microcode source to match the changes made to general worker module.
     new b8c0536  Updated uOP engine to match the changes made to the general worker module (modular subtraction was split into three micro-operations instead of one).
     new 6492883  For the new general worker module to work we need dynamic switching of DSP OPMODE, ALUMODE and CARRYINSEL ports, thus more defined constants.
     new 8f7829c  Tiny cosmetic typo fix ("dst" -> "dsp")
     new 2345e42  Added more meaningful constants to avoid certain hardcoded numbers.
     new c551625  Refactored modular reductor module.
     new 04bc457  Renumbered micro-operations.
     new 76f89d6  The I/O manager has to work in sync with the general worker module. Made the necessary changes to make it work after the general worker update. Also moved debug simulation-time code into a separate file.
     new e68e11a  Update DSP wrapper instance names.
     new c6029af  Refactored MMM recombinator module, accomodated the changes in DSP slice wrapper names.
     new b0cbd33  Refactored the MMM module, now uses meaningful constant names from the include file, not hardcoded widths.
     new c4bee71  Cosmetic change to easily switch tests on/off.
     new 97d5b79  Bump version number.

The 21 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails.  The revisions
listed as "add" were already present in the repository and have only
been added to this reference.

Summary of changes:
 bench/tb_core_full_512.v                           |    6 +-
 rtl/modexpng_core_top_debug.vh                     |  144 +-
 rtl/modexpng_dsp48e1.vh                            |   51 +-
 rtl/modexpng_dsp_array_block.v                     |    8 +-
 rtl/modexpng_dsp_slice_addsub_wrapper_generic.v    |  224 +++
 ... => modexpng_dsp_slice_addsub_wrapper_xilinx.v} |  131 +-
 ...v => modexpng_dsp_slice_mult_wrapper_generic.v} |    2 +-
 ....v => modexpng_dsp_slice_mult_wrapper_xilinx.v} |    2 +-
 ...imitive.vh => modexpng_dsp_slice_primitives.vh} |    6 +-
 rtl/modexpng_general_worker.v                      | 1995 +++++++++-----------
 rtl/modexpng_io_manager.v                          |  364 ++--
 ...png_dsp48e1.vh => modexpng_io_manager_debug.vh} |   18 +-
 rtl/modexpng_microcode.vh                          |   21 +-
 rtl/modexpng_mmm_dual.v                            |  733 +++----
 rtl/modexpng_parameters.vh                         |   10 +-
 rtl/modexpng_recombinator_block.v                  | 1244 ++++++------
 rtl/modexpng_recombinator_cell.v                   |   94 +-
 rtl/modexpng_reductor.v                            |  388 ++--
 rtl/modexpng_uop_engine.v                          |   14 +-
 rtl/modexpng_uop_rom.v                             |  281 +--
 rtl/modexpng_wrapper.v                             |   12 +-
 21 files changed, 3096 insertions(+), 2652 deletions(-)
 create mode 100644 rtl/modexpng_dsp_slice_addsub_wrapper_generic.v
 copy rtl/{modexpng_dsp_slice_wrapper_xilinx.v => modexpng_dsp_slice_addsub_wrapper_xilinx.v} (58%)
 rename rtl/{modexpng_dsp_slice_wrapper_generic.v => modexpng_dsp_slice_mult_wrapper_generic.v} (98%)
 rename rtl/{modexpng_dsp_slice_wrapper_xilinx.v => modexpng_dsp_slice_mult_wrapper_xilinx.v} (99%)
 rename rtl/{modexpng_dsp_slice_primitive.vh => modexpng_dsp_slice_primitives.vh} (85%)
 copy rtl/{modexpng_dsp48e1.vh => modexpng_io_manager_debug.vh} (82%)

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