[Cryptech-Commits] [core/cipher/aes] 17/20: Added missing reset of registers. This fixes CT-01-001 FPGA.

[git at cryptech.is]

This is an automated email from the git hooks/post-receive script.

sra at hactrn.net pushed a commit to branch aes_speed
in repository core/cipher/aes.

commit 9af80907f9d1913cd8cb200eabe5e99cc65021a4
Author: Joachim Strömbergson <joachim at secworks.se>
AuthorDate: Thu Sep 27 15:08:19 2018 +0200

    Added missing reset of registers. This fixes CT-01-001 FPGA.
---
 src/rtl/aes_key_mem.v | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/rtl/aes_key_mem.v b/src/rtl/aes_key_mem.v
index e3aec4b..07e338f 100644
--- a/src/rtl/aes_key_mem.v
+++ b/src/rtl/aes_key_mem.v
@@ -140,12 +140,14 @@ module aes_key_mem(
 
       if (!reset_n)
         begin
-          for (i = 0 ; i < 4 ; i = i + 1)
+          for (i = 0 ; i < 15 ; i = i + 1)
             key_mem [i] <= 128'h0;
 
           rcon_reg         <= 8'h0;
           ready_reg        <= 1'b0;
           round_ctr_reg    <= 4'h0;
+          prev_key0_reg    <= 128'h0;
+          prev_key1_reg    <= 128'h0;
           key_mem_ctrl_reg <= CTRL_IDLE;
         end
       else