[Cryptech-Commits] [core/cipher/aes] branch aes_speed created (now 963e729)

[git at cryptech.is]

This is an automated email from the git hooks/post-receive script.

sra at hactrn.net pushed a change to branch aes_speed
in repository core/cipher/aes.

      at 963e729  Adding restriction to the API to only allow writes to controlling registers. This fixes CT-01-002 FPGA.

This branch includes the following new commits:

     new e389761  Adding inital version of AES core optimized for performance.
     new 0286e46  Adding task to wait for ready to be set. This allows us to measure the number of cycles spent doing operations.
     new c713208  Adding 16 S-boxes to the encipher datapath.
     new 78f091b  Connected the new S-boxes and collapsed the SubBytes operation into one cycle. This provides a speedup for Encipher with 2.1x.
     new 4d36029  Removed the sword counter since it is not needed.
     new ac77ca2  Removed the sbox word mux. Removed ports for sbox access in the encipher datapath since it now has its own sboxes.
     new 8d0777b  Moved the Sbox used for key expansion into the key_mem.
     new 1e9ed58  Cleaned up redundant wires.
     new 0ab3199  Increased number of inverse S-boxes to 16 and removed S-box scheduling.
     new 7a65ca8  Updated core status and implementation details.
     new 6eff2fb  Updated README with implementation results.
     new ea98bf7  Polished the wait_ready task to use defined bit index.
     new a689dcc  Combined all AES round operations into a single operation for a round.
     new a8ce939  Minor cleanup of states and register sizes.
     new 6a39d87  Updated README with latest implementation results and status for the core.
     new c1225cb  Shaved off another cycle for block processing.
     new 9af8090  Added missing reset of registers. This fixes CT-01-001 FPGA.
     new 190bdf4  Reading AES result will be zero when ready is not set.
     new 01d3fb3  Adding testcase that tests the mangling of aes operations by switching from encipher to decipher mid-operation.
     new 963e729  Adding restriction to the API to only allow writes to controlling registers. This fixes CT-01-002 FPGA.

The 20 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails.  The revisions
listed as "add" were already present in the repository and have only
been added to this reference.