[Cryptech-Commits] [core/cipher/aes] 04/21: Connected the new S-boxes and collapsed the SubBytes operation into one cycle. This provides a speedup for Encipher with 2.1x.

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sra at hactrn.net pushed a commit to branch master
in repository core/cipher/aes.

commit 5bf8bd4db261c9823f0e80f6771f3e635c5cbb90
Author: Joachim Strömbergson <joachim at secworks.se>
AuthorDate: Mon May 21 17:39:45 2018 +0200

    Connected the new S-boxes and collapsed the SubBytes operation into one cycle. This provides a speedup for Encipher with 2.1x.
---
 README.md                    |  6 +++---
 src/rtl/aes_encipher_block.v | 49 +++++++++++---------------------------------
 2 files changed, 15 insertions(+), 40 deletions(-)

diff --git a/README.md b/README.md
index 6322084..9504ec1 100644
--- a/README.md
+++ b/README.md
@@ -38,11 +38,11 @@ of cycles to two cycles for each round.
 
 ## Performance and area comparison ##
 Number of cycles for the Cryptech AES core:
-- TBW
+- AES-128 Encipher one block with key expansion: 57
 
 
-Number of cycles for the Cryptech AES core:
-- TBW
+Number of cycles for the Cryptech AES speed core:
+- AES-128 Encipher with key expansion: 27
 
 
 Resources used by the Crypteh AES core:
diff --git a/src/rtl/aes_encipher_block.v b/src/rtl/aes_encipher_block.v
index 29a555e..c1961bd 100644
--- a/src/rtl/aes_encipher_block.v
+++ b/src/rtl/aes_encipher_block.v
@@ -290,6 +290,11 @@ module aes_encipher_block(
       block_w2_we = 1'b0;
       block_w3_we = 1'b0;
 
+      sboxw0 = block_w0_reg;
+      sboxw1 = block_w1_reg;
+      sboxw2 = block_w2_reg;
+      sboxw3 = block_w3_reg;
+
       old_block          = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
       shiftrows_block    = shiftrows(old_block);
       mixcolumns_block   = mixcolumns(shiftrows_block);
@@ -309,33 +314,11 @@ module aes_encipher_block(
 
         SBOX_UPDATE:
           begin
-            block_new = {new_sboxw, new_sboxw, new_sboxw, new_sboxw};
-
-            case (sword_ctr_reg)
-              2'h0:
-                begin
-                  muxed_sboxw = block_w0_reg;
-                  block_w0_we = 1'b1;
-                end
-
-              2'h1:
-                begin
-                  muxed_sboxw = block_w1_reg;
-                  block_w1_we = 1'b1;
-                end
-
-              2'h2:
-                begin
-                  muxed_sboxw = block_w2_reg;
-                  block_w2_we = 1'b1;
-                end
-
-              2'h3:
-                begin
-                  muxed_sboxw = block_w3_reg;
-                  block_w3_we = 1'b1;
-                end
-            endcase // case (sbox_mux_ctrl_reg)
+            block_new = {new_sboxw0, new_sboxw1, new_sboxw2, new_sboxw3};
+            block_w0_we = 1'b1;
+            block_w1_we = 1'b1;
+            block_w2_we = 1'b1;
+            block_w3_we = 1'b1;
           end
 
         MAIN_UPDATE:
@@ -427,8 +410,6 @@ module aes_encipher_block(
           num_rounds = AES128_ROUNDS;
         end
 
-      sword_ctr_inc = 1'b0;
-      sword_ctr_rst = 1'b0;
       round_ctr_inc = 1'b0;
       round_ctr_rst = 1'b0;
       ready_new     = 1'b0;
@@ -453,7 +434,6 @@ module aes_encipher_block(
         CTRL_INIT:
           begin
             round_ctr_inc = 1'b1;
-            sword_ctr_rst = 1'b1;
             update_type   = INIT_UPDATE;
             enc_ctrl_new  = CTRL_SBOX;
             enc_ctrl_we   = 1'b1;
@@ -461,18 +441,13 @@ module aes_encipher_block(
 
         CTRL_SBOX:
           begin
-            sword_ctr_inc = 1'b1;
             update_type   = SBOX_UPDATE;
-            if (sword_ctr_reg == 2'h3)
-              begin
-                enc_ctrl_new  = CTRL_MAIN;
-                enc_ctrl_we   = 1'b1;
-              end
+            enc_ctrl_new  = CTRL_MAIN;
+            enc_ctrl_we   = 1'b1;
           end
 
         CTRL_MAIN:
           begin
-            sword_ctr_rst = 1'b1;
             round_ctr_inc = 1'b1;
             if (round_ctr_reg < num_rounds)
               begin