[Cryptech-Commits] [core/cipher/aes] branch master updated (1ad1120 -> 9590720)

[git at cryptech.is]

This is an automated email from the git hooks/post-receive script.

sra at hactrn.net pushed a change to branch master
in repository core/cipher/aes.

    from 1ad1120  For completeness sake added API hardening to the aes core too. The AES core has been replaced with the aes_speed core but is still available as a separate repo.
     new 24b85c9  Adding inital version of AES core optimized for performance.
     new f3314ff  Adding task to wait for ready to be set. This allows us to measure the number of cycles spent doing operations.
     new cbf595b  Adding 16 S-boxes to the encipher datapath.
     new 5bf8bd4  Connected the new S-boxes and collapsed the SubBytes operation into one cycle. This provides a speedup for Encipher with 2.1x.
     new b25a4d4  Removed the sword counter since it is not needed.
     new 1da0928  Removed the sbox word mux. Removed ports for sbox access in the encipher datapath since it now has its own sboxes.
     new 577a8c7  Moved the Sbox used for key expansion into the key_mem.
     new 2fc6cc9  Cleaned up redundant wires.
     new 61f2ceb  Increased number of inverse S-boxes to 16 and removed S-box scheduling.
     new 6baf074  Updated core status and implementation details.
     new c596c2f  Updated README with implementation results.
     new 3bc7454  Polished the wait_ready task to use defined bit index.
     new f94d773  Combined all AES round operations into a single operation for a round.
     new 59c5def  Minor cleanup of states and register sizes.
     new 74e0f67  Updated README with latest implementation results and status for the core.
     new fd40ab8  Shaved off another cycle for block processing.
     new 1ef4aa6  Added missing reset of registers. This fixes CT-01-001 FPGA.
     new 717f11e  Reading AES result will be zero when ready is not set.
     new 00f01ac  Adding testcase that tests the mangling of aes operations by switching from encipher to decipher mid-operation.
     new 833921d  Adding restriction to the API to only allow writes to controlling registers. This fixes CT-01-002 FPGA.
     new 9590720  Clean-up ill-advised fork of core/cipher/aes.

The 21 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails.  The revisions
listed as "add" were already present in the repository and have only
been added to this reference.


Summary of changes:
 README.md                       |   74 ++-
 src/model/python/aes.py         | 1058 ---------------------------------------
 src/model/python/aes_key_gen.py |  568 ---------------------
 src/model/python/rcon.py        |  586 ----------------------
 src/rtl/aes.v                   |   23 +-
 src/rtl/aes_core.v              |   45 +-
 src/rtl/aes_decipher_block.v    |  196 ++------
 src/rtl/aes_encipher_block.v    |  209 ++------
 src/rtl/aes_key_mem.v           |   22 +-
 src/tb/tb_aes.v                 |  100 ++--
 src/tb/tb_aes_core.v            |   89 ++--
 src/tb/tb_aes_decipher_block.v  |   10 +-
 src/tb/tb_aes_encipher_block.v  |   27 +-
 src/tb/tb_aes_key_mem.v         |   11 +-
 toolruns/Makefile               |   50 +-
 15 files changed, 284 insertions(+), 2784 deletions(-)
 delete mode 100755 src/model/python/aes.py
 delete mode 100755 src/model/python/aes_key_gen.py
 delete mode 100644 src/model/python/rcon.py