[Cryptech-Commits] [user/sra/aes_merged] 44/45: For completeness sake added API hardening to the aes core too. The AES core has been replaced with the aes_speed core but is still available as a separate repo.

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sra at hactrn.net pushed a commit to branch master
in repository user/sra/aes_merged.

commit 1ad1120086e4d9f6599555ed2ea6a54994ec8e1b
Author: Joachim Strömbergson <joachim at secworks.se>
AuthorDate: Tue Oct 23 10:42:00 2018 +0200

    For completeness sake added API hardening to the aes core too. The AES core has been replaced with the aes_speed core but is still available as a separate repo.
---
 src/rtl/aes.v         | 26 +++++++++++++++-----------
 src/rtl/aes_key_mem.v |  2 +-
 2 files changed, 16 insertions(+), 12 deletions(-)

diff --git a/src/rtl/aes.v b/src/rtl/aes.v
index 0d719d2..4f668bc 100644
--- a/src/rtl/aes.v
+++ b/src/rtl/aes.v
@@ -236,20 +236,23 @@ module aes(
         begin
           if (we)
             begin
-              if (address == ADDR_CTRL)
+              if (core_ready)
                 begin
-                  init_new = write_data[CTRL_INIT_BIT];
-                  next_new = write_data[CTRL_NEXT_BIT];
-                end
+                  if (address == ADDR_CTRL)
+                    begin
+                      init_new = write_data[CTRL_INIT_BIT];
+                      next_new = write_data[CTRL_NEXT_BIT];
+                    end
 
-              if (address == ADDR_CONFIG)
-                config_we = 1'b1;
+                  if (address == ADDR_CONFIG)
+                    config_we = 1'b1;
 
-              if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7))
-                key_we = 1'b1;
+                  if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7))
+                    key_we = 1'b1;
 
-              if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK3))
-                block_we = 1'b1;
+                  if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK3))
+                    block_we = 1'b1;
+                end
             end // if (we)
 
           else
@@ -267,7 +270,8 @@ module aes(
               endcase // case (address)
 
               if ((address >= ADDR_RESULT0) && (address <= ADDR_RESULT3))
-                tmp_read_data = result_reg[(3 - (address - ADDR_RESULT0)) * 32 +: 32];
+                if (core_ready)
+                  tmp_read_data = result_reg[(3 - (address - ADDR_RESULT0)) * 32 +: 32];
             end
         end
     end // addr_decoder
diff --git a/src/rtl/aes_key_mem.v b/src/rtl/aes_key_mem.v
index b26b870..f57d4dd 100644
--- a/src/rtl/aes_key_mem.v
+++ b/src/rtl/aes_key_mem.v
@@ -138,7 +138,7 @@ module aes_key_mem(
 
       if (!reset_n)
         begin
-          for (i = 0 ; i < 14 ; i = i + 1)
+          for (i = 0 ; i < 15 ; i = i + 1)
             key_mem [i] <= 128'h0;
 
           prev_key0_reg    <= 128'h0;